Standardized FPGA Logic Drive Packaging for Lower NRE Costs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high Non-Recurring Engineering (NRE) costs and inefficiencies of transitioning from Field Programmable Gate Arrays (FPGA) to Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips for advanced semiconductor technology nodes hinder innovation and scalability in logic drives.
Innovation Solution
Utilizing a standardized commodity logic drive comprising plural FPGA IC chips and non-volatile memory IC chips, which reduces NRE costs and enables field programming for various applications, allowing developers to write software codes for specific functionalities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA IC chips are used for advanced semiconductor technology nodes, then adaptability and ease of operation are improved, but manufacturing cost and fabrication yield deteriorate
Solution Approach 1:
The patent segments the logic drive into multiple standardized commodity FPGA IC chips packaged together in a multi-chip package. This allows the system to use multiple smaller, more manufacturable chips instead of a single large custom ASIC, thereby reducing manufacturing cost while maintaining adaptability through the programmable nature of FPGAs.
Solution Approach 2:
The patent employs universal standardized commodity FPGA IC chips that can be programmed to perform different logic functions. These FPGAs replace application-specific custom ASICs, providing the same adaptability and versatility while benefiting from the economies of scale and standardized manufacturing processes of commodity FPGA production.
2Manufacturing precision
If custom ASIC or COT IC chips are designed for specific applications, then manufacturing precision and performance are improved, but Non-Recurring Engineering costs and device complexity increase
Solution Approach 1:
The patent uses dynamically reconfigurable FPGA logic blocks that can be programmed in the field to implement different logic functions. This dynamic programmability replaces static custom ASIC designs, achieving the same application-specific performance while eliminating the high NRE costs and design complexity associated with custom chip development.
Solution Approach 2:
The patent uses standardized commodity FPGA IC chips as copies or approximations of custom ASIC designs. Instead of designing and fabricating expensive custom ASICs, the system uses off-the-shelf FPGAs that can be programmed to replicate the desired logic functionality, thereby reducing NRE costs and device complexity while maintaining performance.
3Adaptability or versatility
If FPGA IC chips are used instead of ASIC, then adaptability is improved, but power consumption and semiconductor chip size increase
Solution Approach 1:
The patent uses multiple standardized FPGA IC chips in a multi-chip package rather than a single large FPGA. This partial approach allows the system to achieve the required adaptability by distributing the logic function across multiple smaller chips, which can individually consume less power and occupy smaller chip areas, while collectively providing the necessary computational capability.
Data Source
AI summary
A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; afield-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.