FPGA Logic Mapping for Single-Event Upset Mitigation
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Solution Overview
Problem
Programmable integrated circuits, such as FPGAs, are susceptible to single-event upsets due to radiation, which can alter the functionality of the circuit and cause failures, particularly in sub-100 nanometer technologies where capacitance at storage nodes is reduced, making larger configuration memory cells more prone to errors.
Innovation Solution
A circuit design tool preferentially maps combinatorial logic functions onto LUT-type lookup tables instead of LUTRAM-type lookup tables, which are more susceptible to single-event upsets, to reduce the failure rate by increasing the usage percentage of LUT-type lookup tables during the implementation of circuit designs for programmable ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If LUTRAM-type lookup tables are used to implement combinatorial logic functions, then the circuit design flexibility and functionality are improved, but the single-event failure rate increases due to higher susceptibility to radiation-induced errors
Solution Approach 1:
The patent applies local quality by differentiating between two types of lookup tables (LUT-type and LUTRAM-type) with different radiation susceptibility characteristics, and selectively mapping combinatorial logic functions to the more radiation-hard LUT-type tables. This creates local optimization where critical logic functions are placed in more reliable locations within the FPGA architecture.
Solution Approach 2:
The patent changes the mapping parameter (percentage of logic functions mapped to LUT-type vs LUTRAM-type tables) to control the trade-off between design flexibility and radiation hardness. By adjusting this parameter, designers can optimize the single-event failure rate while maintaining acceptable circuit functionality.
2Reliability
If LUT-type lookup tables are preferentially used for combinatorial logic functions, then the single-event failure rate is reduced, but the device complexity increases due to non-uniform resource utilization
Solution Approach 1:
The patent implements partial action by mapping only a threshold percentage of combinatorial logic functions to LUT-type lookup tables, rather than forcing all logic functions to use this table type. This partial application reduces the single-event failure rate for critical functions while avoiding the excessive complexity that would result from universal application.
3Adaptability or versatility
If configuration memory cells are enlarged to store more logic states, then the logic functionality is improved, but the susceptibility to single-event upsets increases due to larger cell size
Solution Approach 1:
The patent segments the lookup table resources into two distinct types (LUT-type and LUTRAM-type) with different configuration memory cell characteristics. By dividing the logic function mapping across these segmented resources, the system can place radiation-sensitive functions in more robust LUT-type tables while maintaining the functionality benefits of LUTRAM-type tables for other functions.
Data Source
AI summary
In an example, a method of implementing a circuit design for a programmable integrated circuit (IC) begins by identifying combinatorial logic functions of the circuit design. The method maps, according to a first constraint, a first threshold percentage of the combinatorial logic functions onto a first type of lookup tables (LUTs) of the programmable IC in favor of second type of LUTs of the programmable IC, the second type of LUTs being more susceptible to single event upsets than the first type of LUTs. The method generates a first physical implementation of the circuit design for the programmable IC based on the mapping.