Coupled FPGA Lookup Tables for Rapid Configuration Switching
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Solution Overview
Problem
Existing field programmable gate arrays (FPGAs) are limited in their ability to rapidly change lookup table configurations, resulting in slow operation frequency changes, typically occurring only hundreds of times per second, due to the need to cycle power for each configuration modification.
Innovation Solution
Coupling logic blocks in FPGAs allows direct transfer of lookup table configurations between adjacent blocks, utilizing non-volatile CMOS-based memory cells to reduce power consumption and enable faster operation frequency changes, potentially up to millions or billions of times per second, by leveraging a common clock signal to update configurations without power cycling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If lookup table configurations are loaded by cycling power for each configuration modification, then configuration changes can be made, but the operation frequency changes are slow (hundreds of times per second)
Solution Approach 1:
The patent pre-loads configuration data into on-chip memory blocks before operation. This preliminary action allows the FPGA to switch between configurations rapidly by simply activating different pre-loaded memory blocks, eliminating the need for time-consuming power cycling to load configurations.
Solution Approach 2:
The patent replaces the mechanical power cycling method with an electronic memory-based system. Instead of physically cycling power to load configurations, the system uses electronic memory blocks that can be rapidly switched between different configuration states, enabling much faster operation frequency changes.
2Adaptability or versatility
If power is cycled for each configuration modification, then configurations can be updated, but power consumption increases
Solution Approach 1:
Configuration data is pre-loaded into on-chip memory blocks before operation. This preliminary action enables rapid configuration switching without power cycling, as the system can simply activate different pre-loaded memory blocks, thereby maintaining adaptability while significantly reducing power consumption.
Solution Approach 2:
The patent changes the operational parameters of the FPGA by using different memory blocks to store different configuration states. By switching between pre-loaded memory blocks with different configuration data, the system achieves configuration updates without the energy-intensive power cycling process.
3Ease of operation
If lookup tables are loaded across multiple logic blocks using traditional methods, then configurations are applied, but the process is time-consuming and requires power cycling
Solution Approach 1:
The patent divides the configuration loading process into separate on-chip memory blocks, each capable of storing a complete configuration set. This segmentation allows different logic blocks to have their configurations independently managed and switched, enabling parallel configuration updates without sequential power cycling across the entire device.
Solution Approach 2:
The patent replaces the traditional mechanical power cycling method with an electronic memory-based system. Configuration data is stored in on-chip memory blocks and can be rapidly switched between logic blocks through electronic signals, eliminating the time-consuming power cycling process and enabling fast configuration propagation across the FPGA.
Data Source
AI summary
A reconfigurable field programmable gate array (FPGA) includes: a first logic block having a first lookup table; and a second logic block having a second lookup table, wherein the first logic block is coupled to the second logic block, in which the first logic block is configured to pass, upon a clock cycle of the FPGA, data about a lookup table configuration stored in the first lookup table to the second logic block.