FPGA LUT Layout Using Nonvolatile Memory for Multi-Application Switching

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Solution Overview

Problem

Conventional Look Up Tables (LUTs) in Field Programmable Gate Arrays (FPGAs) lose data when power is interrupted and require reprogramming for each application, leading to inefficient use of resources and excessive FPGA size when accommodating multiple applications.

Innovation Solution

Incorporating nonvolatile memory elements in LUTs that can be selectively programmed and read using application-specific signals, allowing for pre-programming of multiple applications without the need for frequent reconfiguration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional SRAM-based LUTs are used, then the LUT is easy to implement logic circuits, but data is lost when power is interrupted requiring reprogramming

Engineering Contradiction:
Improveease to implement logic circuitsVSAvoiddata retention without power
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent changes the fundamental parameter of memory technology from volatile SRAM to nonvolatile memory elements, enabling data retention without power while maintaining logic circuit functionality through the same LUT architecture

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent enables preliminary programming of multiple applications into nonvolatile memory elements before operation, so that when power is restored or application switching is needed, the LUT can immediately use pre-programmed data without reprogramming delays

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If the FPGA includes multiple LUTs for multiple applications, then reprogramming is avoided, but the FPGA size becomes excessive

Engineering Contradiction:
Improvereprogramming timeVSAvoidFPGA size
Core Design Contradiction:
Loss of timeVSArea of stationary object

Solution Approach 1:

The patent makes each LUT universal by enabling it to store multiple applications simultaneously in nonvolatile memory elements, allowing a single LUT to serve multiple applications without requiring duplicate LUTs for each application

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent enables preliminary programming of multiple applications into the same LUT's nonvolatile memory elements, so that application switching can occur instantly without reprogramming or requiring additional standby LUTs

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If SRAMs are reprogrammed for application switching, then the LUT can serve different applications, but power consumption increases and reprogramming is required

Engineering Contradiction:
Improveapplication switching capabilityVSAvoidpower consumption during reprogramming
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the memory technology parameter from volatile SRAM to nonvolatile memory, enabling application switching by simply changing selection signals rather than physically reprogramming, which eliminates high power consumption associated with SRAM reprogramming

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent enables all applications to be pre-programmed into the LUT's nonvolatile memory elements before operation, so that application switching during operation requires only signal changes without additional programming power consumption

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10924117B2Method for designing an FPGA
Publication Date: 2021.02.16 SK HYNIX INC
  • US10924117B2 patent drawing
  • US10924117B2 patent drawing
  • US10924117B2 patent drawing

AI summary

A method for designing an FPGA may include determining blocks required for each of a plurality of applications; determining a size of the FPGA accommodating the determined blocks for each of the plurality of applications; and laying out the determined blocks for each of the plurality of applications in a block array of the FPGA.