FPGA Logic Module Using LUT Multiplexer Tree for Faster Adders
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Solution Overview
Problem
Existing adder circuits for field-programmable gate arrays (FPGAs) face inefficiencies in implementing arithmetic functions due to substantial delay and additional circuitry requirements, limiting flexibility and performance.
Innovation Solution
A logic module with an N-level tree of 2:1 multiplexers is introduced, allowing for flexible configuration of inputs and internal signal tapping to reduce delay and circuitry needs, replacing dedicated XOR gates with multiplexers and optimizing carry propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional adder circuits are used in FPGA, then arithmetic functions can be implemented, but substantial delay and additional circuitry requirements occur
Solution Approach 1:
The LUT is designed to serve dual purposes: performing logic functions through its normal operation and performing adder functions by tapping internal signals. The same LUT infrastructure (multiplexer tree) is used for both logic computation and arithmetic addition, eliminating the need for separate dedicated adder circuitry and reducing overall delay.
Solution Approach 2:
An internal signal from the LUT's multiplexer tree is tapped and used as an intermediary to generate the G (generate) signal for the carry-lookahead logic. This intermediary signal allows the circuit to leverage existing LUT computation results to accelerate carry propagation without requiring additional independent adder stages.
2Productivity
If traditional adder circuits are used in FPGA, then arithmetic functions can be implemented, but additional circuitry requirements increase
Solution Approach 1:
The LUT is designed to serve dual purposes: performing logic functions through its normal operation and performing adder functions by tapping internal signals. The same LUT infrastructure (multiplexer tree) is used for both logic computation and arithmetic addition, eliminating the need for separate dedicated adder circuitry and reducing overall delay.
Solution Approach 2:
The adder functionality is merged with the LUT structure by tapping internal signals from the multiplexer tree. The G signal generation is combined with the LUT's existing signal routing, and the carry-lookahead logic shares resources with the LUT output stage, reducing total circuitry requirements.
3Speed
If carry out signal is produced by 2:1 multiplexer from inputs P, G, and CI, then carry propagation can be achieved, but circuit complexity increases
Solution Approach 1:
The LUT output stage multiplexer is made multi-functional: it normally selects between logic function outputs, but when configured for addition, it selects between P and G signals to drive the carry-lookahead logic. This eliminates the need for a separate dedicated carry multiplexer, reducing circuit complexity while maintaining fast carry propagation.
Solution Approach 2:
The carry output selection function is merged with the LUT's output multiplexer. The same multiplexer that normally outputs the LUT's logic result is also used to select the carry signal (P or G) based on configuration, consolidating functions and reducing overall circuit complexity.
Data Source
AI summary
A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer.