FPGA Macro Scheduling for Multi-Client Resource Sharing
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Solution Overview
Problem
Existing datacenters using field programmable gate array (FPGA) devices allocate hardware resources inefficiently, especially when serving multiple independent clients, as they lack effective mechanisms for resource sharing and optimization.
Innovation Solution
Implementing a macro scheduler that organizes FPGA hardware resources into logical units called macro components, enabling virtualization through resource sharing, time multiplexing, and optimization by using local and standalone macro schedulers that allocate and schedule these resources efficiently across multiple FPGA devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional FPGA allocation methods are used, then each client gets dedicated hardware resources, but resource utilization efficiency deteriorates when serving multiple clients
Solution Approach 1:
The patent segments FPGA hardware resources into discrete macro components (logic blocks, memory blocks, I/O blocks, etc.) that can be independently allocated and shared among multiple clients. This segmentation enables fine-grained resource sharing while maintaining efficient utilization, resolving the contradiction between productivity and device complexity.
Solution Approach 2:
The patent creates a universal macro scheduler that can allocate the same hardware resources to different clients at different times, making the FPGA resources multi-functional. The system manages multiple clients sharing the same physical hardware through time-multiplexed allocation, improving resource utilization efficiency without requiring dedicated resources for each client.
2Productivity
If hardware resources are shared among multiple clients, then resource utilization improves, but scheduling and allocation complexity increases
Solution Approach 1:
The scheduling mechanism is segmented into a hierarchical structure with a top-level macro scheduler that manages client allocations and lower-level component schedulers that manage specific hardware resources. This segmentation of the scheduling function reduces overall complexity by distributing scheduling decisions across multiple manageable components rather than requiring a single complex scheduler.
Solution Approach 2:
The patent introduces an intermediary macro scheduler layer between clients and hardware resources that abstracts the complexity of resource sharing. This intermediary manages all allocation decisions, handles client requests, and coordinates resource usage, thereby simplifying the overall system architecture while enabling efficient multi-client resource sharing.
3Productivity
If dedicated FPGA resources are allocated to each client, then resource allocation is simple, but overall system throughput deteriorates due to idle resources
Solution Approach 1:
The macro scheduler implements periodic allocation cycles where hardware resources are systematically reassigned to different clients in time-multiplexed fashion. During each allocation period, resources are dedicated to specific clients, then reassigned in subsequent periods, ensuring continuous utilization and eliminating idle time while maintaining simple allocation rules within each period.
Solution Approach 2:
The patent ensures continuity of useful action by continuously allocating hardware resources to productive tasks across different clients without idle periods. The macro scheduler maintains a continuous stream of resource utilization by seamlessly transitioning resources between clients, eliminating the idle time that occurs with dedicated allocations when clients have varying workload demands.
Data Source
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AI summary
A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.