FPGA Technology Mapping Delay Reduction via Critical Fan-In Node Replication
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Solution Overview
Problem
Current FPGA technology mapping techniques incur delays due to critical path bottlenecks, where non-critical signals must wait for signals on the critical path, leading to inefficiencies in logic mapping and increased LUT consumption.
Innovation Solution
The proposed solution involves identifying critical fan-in nodes using a Critical Path Identifier, replicating their logic with a Logic Replicator, performing parallel computations on these nodes and non-critical signals using a Parallel Computer, and selecting the output at the last critical fan-in node with an Output Selector to reduce mapping delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If logic is mapped into LUTs following traditional technology mapping techniques, then the mapping process is simple and area is minimized, but critical path delay increases because non-critical signals must wait for signals on the critical path
Solution Approach 1:
The mapping process is segmented into distinct phases: critical path identification, logic replication for critical fan-in nodes, parallel computation execution, and output selection. This segmentation allows each phase to be optimized independently, reducing overall mapping delay while managing complexity through structured decomposition of the mapping workflow
Solution Approach 2:
Critical fan-in nodes are identified and their logic is replicated in advance before the actual mapping computation. This preliminary replication prepares the structure for parallel computation, enabling non-critical signals to proceed without waiting for critical path signals during the main mapping process, thereby reducing mapping delay
2Loss of time
If logic is replicated for parallel computation on critical fan-in nodes, then mapping delay is reduced, but LUT consumption and area increase
Solution Approach 1:
Logic replication is applied selectively only to critical fan-in nodes identified through critical path analysis, rather than uniformly to all nodes. This localized approach ensures that area overhead is concentrated only where it provides delay reduction benefit, minimizing unnecessary LUT consumption while achieving the goal of reducing mapping delay in critical regions
Solution Approach 2:
The system changes the structural parameter of the logic network by replicating critical fan-in nodes, transforming a sequential critical path structure into a parallel structure. This parameter change (from sequential to parallel) reduces the time parameter (mapping delay) at the cost of increasing the quantity parameter (LUT consumption), achieving an optimized trade-off
3Speed
If critical path optimization is focused exclusively, then delay on critical path is reduced, but overall circuit area increases due to replicated logic
Solution Approach 1:
A multiplexer is introduced as an intermediary component that selects between replicated logic outputs based on the actual input values. This intermediary allows the circuit to maintain multiple parallel computation paths for speed optimization while using a single selected output, thereby reducing critical path delay without proportionally increasing the area of functional logic
Data Source
AI summary
The present invention relates to a system for reducing the delay during technology mapping in FPGA that comprises locating and replicating the critical fan-in nodes in the mapping logic. Parallel computation is performed on the replicated nodes followed by selection of the output. The delay reduction approach in the present invention gives a highly efficient logic implementation when delay is the prime concern and area can be afforded to be expanded. The technique relies on replicating logic and performing parallel computation on delay critical LUT's.