Reconfigurable FPGA Market Data Decoder via Parallel FSM

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Solution Overview

Problem

Current market data processing systems face limitations in processing high volumes of data due to sequential decoding methods, leading to bandwidth limitations and high latency, especially when using FPGAs, which are difficult to update for format changes.

Innovation Solution

A decoding device and method that uses a code generation approach with a Finite State Machine and tokenizer to process market data streams in parallel, allowing easy adaptation to format changes by updating the description file and firmware, enabling high-performance decoding up to 10 GB/s with low latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If sequential decoding is used in software or hardware, then implementation simplicity is maintained, but processing speed and throughput are limited

Engineering Contradiction:

Improvedecoding throughputVSAvoiddecoder architecture complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The decoder is segmented into multiple independent decoding units that can process different data streams in parallel. Each decoding unit handles a portion of the input data simultaneously, transforming the single-threaded sequential process into a multi-threaded parallel architecture, thereby increasing throughput without proportionally increasing overall system complexity

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from one-dimensional sequential processing to two-dimensional parallel processing by introducing multiple decoding units operating simultaneously. This dimensional expansion allows the system to process multiple messages per clock cycle, achieving high throughput while maintaining manageable complexity through standardized unit replication

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If FPGAs are used for parallel processing, then throughput increases, but adaptability to format changes decreases

Engineering Contradiction:

Improvedata processing speedVSAvoidformat update ease

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The FPGA decoder employs dynamic reconfiguration capabilities that allow the decoding logic to be updated and adapted to different data formats without hardware replacement. The system can dynamically adjust its decoding behavior based on format requirements, combining the speed of hardware parallel processing with the flexibility of software-like adaptability

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The decoder is designed as a universal platform that can handle multiple data formats through a common parallel processing architecture. By implementing format-agnostic decoding units that can be configured for different protocols, the system achieves both high processing speed and broad format compatibility without sacrificing adaptability

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If software decoders are used, then adaptability to format changes is easy, but bandwidth limitations and latency increase

Engineering Contradiction:

Improveformat modification easeVSAvoiddecoding speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent replaces the mechanical sequential execution model of software decoders with a hardware-based parallel processing system. By substituting software interpretation with dedicated hardware decoding units that operate in parallel, the system achieves speeds comparable to hardware while maintaining format adaptability through reconfigurable logic

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Productivity

If hardware transfers are used for data processing, then processing speed improves, but latency increases due to multiple transfers

Engineering Contradiction:

Improveprocessing throughputVSAvoidtransfer latency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent merges the data transfer and decoding operations into a unified parallel processing pipeline. By combining these previously separate sequential steps into an integrated hardware architecture where decoding units directly process incoming data streams without intermediate storage and retrieval cycles, the system eliminates transfer latency while maintaining high throughput

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS10672014B2Method and a device for decoding data streams in reconfigurable platforms

Publication Date: 2020.06.02 EXEGY SA

AI summary

A decoding device is implemented on an integrated circuit, for decoding a market data input stream received in a given data representation format. The decoding device comprises an engine built around a finite state machine, the engine being generated from at least one description file and configured to perform the following steps, in a current state of the finite state machine: i) dividing the market data input stream into a number of tokens and reading a set of tokens, ii) accumulating the set of read tokens in internal registers, iii) generating output commands from the tokens accumulated in the internal registers depending on a condition related to the tokens accumulated in the internal registers, and iv) selecting the next state of the Finite State Machine state based on a triggering condition.