FPGA Circuit for Mass Quote Message Processing
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Solution Overview
Problem
Financial exchanges face challenges in processing high volumes of messages, particularly mass quote updates, which are limited by conventional server and network speeds, leading to throttling and increased latency, affecting market makers' ability to maintain accurate prices and competitiveness.
Innovation Solution
The implementation of an FPGA or ASIC integrated circuit component configured to receive, process, and store various message types, including mass quote messages, away market prices, and trading state messages, enabling faster processing and generation of market data, and providing accurate quote status updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional servers and networks are used to process mass quote messages, then system complexity remains manageable, but processing capacity is limited and latency increases
Solution Approach 1:
The patent replaces conventional server-based software processing with hardware-based Field Programmable Gate Array (FPGA) circuits. This substitution enables parallel processing of mass quote messages at the hardware level, dramatically increasing processing capacity from thousands to millions of messages per second while reducing latency from milliseconds to microseconds.
Solution Approach 2:
The patent divides the processing system into multiple FPGA devices that can independently process different portions of the message stream. Each FPGA is configured with specific processing logic for particular message types, allowing the system to handle diverse message formats simultaneously through functional segmentation.
2Loss of time
If conventional processing systems are used, then ease of operation is maintained, but latency increases during high market activity
Solution Approach 1:
The patent replaces software-based processing on conventional servers with hardware-based FPGA circuits that execute processing logic in parallel. This hardware acceleration reduces message processing latency from milliseconds to microseconds, enabling the system to keep pace with high-frequency market movements while maintaining high processing capacity.
Solution Approach 2:
The patent pre-configures FPGA circuits with processing logic for anticipated message types including mass quote messages, order messages, and market data feeds. This preliminary configuration allows the system to immediately process incoming messages without interpretation delays, minimizing latency during high-activity periods.
Data Source
AI summary
A distributed computer system includes a matcher server that stores an order book of pending orders and a gateway that routes an order message to the matcher server for matching. The gateway also receives individual quote messages bundled into a mass quote message, each individual quote message including a price value for one of a plurality of different instrument identifiers. The gateway routes the mass quote message to a field programmable gate array (FPGA) circuit without involving the matcher server. The FPGA parses and stores data for each individual quote message to a data structure located in the memory of the FPGA. The parsed data is organized in the data structure according to both the instrument identifier and a client identifier that corresponds to a client that sent the mass quote message. The FPGA receives away market feed messages that each include a price value and a corresponding instrument identifier without first being routed through the matcher server or the gateway and updates the data structure. The FPGA delivers, in response to a query sent as part of the matching process performed on the matcher server for the instrument, information stored in the data structure regarding the instrument.