FPGA Configuration via Master Chip and Conversion Tool
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current automatic test equipment (ATE) for ICs is inefficient in testing field programmable gate arrays (FPGAs) due to complex configuration processes, especially for FPGAs with a large number of pins, as it requires manual modification of configuration data and is not suited for repeated configuration and testing, leading to high costs and reduced ease of use.
Innovation Solution
A method and system for configuring and testing FPGAs using a bumping process, where configuration code streams are stored on mass memories, read in real-time by a master FPGA, and automatically loaded onto the FPGA chip via an external test interface, enabling fast, repeatable configuration and testing without powering off, using an automatic test equipment (ATE) test module, a test and configuration board, and a computer to create and convert configuration files into test signal source files recognizable by ATE.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If manual modification of configuration data is used for ATE testing, then configuration can be achieved, but the process becomes complex and time-consuming
Solution Approach 1:
The patent introduces an intermediary conversion tool that automatically transforms ATE-executable configuration data into FPGA-specific configuration files. This mediator eliminates the need for manual modification, reducing both operational complexity and time requirements while maintaining full automation capability.
Solution Approach 2:
The system enables self-service through automated configuration file generation. The conversion tool automatically processes ATE test data and generates the required FPGA configuration files without human intervention, making the process efficient and scalable for large numbers of pins.
2Productivity
If configuration data are manually modified for ATE-executable format, then testing can be performed, but configuration time increases significantly
Solution Approach 1:
The patent implements preliminary action by pre-converting ATE configuration data into FPGA-specific formats before actual testing begins. The conversion tool prepares all necessary configuration files in advance, eliminating time-consuming manual modifications during the testing phase and enabling rapid repeated configuration.
Solution Approach 2:
The manual mechanical process of configuration data modification is replaced with an automated computational conversion system. The conversion tool uses algorithmic processing to transform configuration data, dramatically reducing configuration time from manual operations to automated instant generation.
3Adaptability or versatility
If dedicated control chip and CF card are used for system ACE configuration, then configuration can be achieved, but system cost and space requirements increase
Solution Approach 1:
The patent applies universality by using a general-purpose conversion tool that can handle multiple configuration formats and FPGA types without requiring dedicated control chips or CF cards. This multi-functional approach reduces system complexity and cost while maintaining broad configuration capability across different FPGA devices.
Solution Approach 2:
The patent extracts the configuration control functionality from dedicated hardware components (control chip and CF card) and relocates it to a software-based conversion tool. This extraction eliminates the need for additional hardware, reducing both system cost and space requirements while preserving full configuration capability.
Data Source
AI summary
A configuration and testing method and system for an FPGA chip using a bumping process are disclosed, the method includes creating configuration files for an FPGA chip under test and storing them in a memory; reading, by a master FPGA, a configuration code stream of corresponding configuration codes from the mass memory, configuring the FPGA chip under test via an external test interface, and determining whether the configuration is successful; if the configuration is successful, converting the configuration code stream into a test signal source file that is recognizable, executable and reusable by multiple pieces of test equipment by a developed algorithm and a conversion tool; and automatically loading the test signal source file onto the FPGA chip under test in real time by advanced test equipment.