FPGA Math Block Routing with Reusable Shadow Soft Logic
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Solution Overview
Problem
Existing FPGA math blocks, primarily composed of hard logic, are limited in configurability and waste resources when not used, as they occupy area and consume power without contributing to general-purpose applications, and supplementary functionality is inefficiently implemented with additional hard logic or unpredictable soft logic connections.
Innovation Solution
The architecture integrates a hard logic block with dedicated connections to shadow soft logic and general-purpose routing, allowing shadow soft logic to be used for general purposes when the hard logic is not employed, and providing supplementary functionality through dedicated connections with predictable delays, reducing resource waste and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hard logic blocks are used for math operations, then speed and power efficiency are improved, but configurability and area utilization deteriorate when the block is not used
Solution Approach 1:
The hard logic block is designed to perform multiple functions: it can operate as a dedicated math block for high-speed arithmetic operations, or be reconfigured as shadow soft logic for general-purpose logic functions. This multi-functionality allows the same physical hardware to serve different purposes based on configuration, improving both speed efficiency and adaptability.
2Use of energy by moving object
If hard logic blocks are used for math operations, then power efficiency is improved, but area waste increases when the block is not used
Solution Approach 1:
When the hard logic block is not needed for math operations, it can be discarded as a math block and recovered as shadow soft logic for general-purpose use. This recovery mechanism ensures that the area is not wasted but rather repurposed for other functions, eliminating the area waste problem while maintaining power efficiency when the math block is actively used.
3Adaptability or versatility
If additional hard logic is added for supplementary functionality, then functional completeness is improved, but area and power waste increase when supplementary functionality is not needed
Solution Approach 1:
The supplementary functionality is implemented dynamically through shadow soft logic that can be selectively activated. Instead of having static additional hard logic always present and consuming power, the shadow soft logic provides the same functional completeness only when needed, allowing the system to adapt its functionality and power consumption based on operational requirements.
4Area of stationary object
If soft logic connections are used for supplementary functionality, then area efficiency is improved, but speed and predictability deteriorate
Solution Approach 1:
Dedicated intermediate connections are provided between the hard logic block and shadow soft logic, serving as a mediator that ensures fast and predictable signal propagation. These dedicated pathways act as intermediaries that bridge the hard logic and soft logic, maintaining high speed performance while allowing the shadow soft logic to provide area-efficient supplementary functionality.
Data Source
AI summary
An architecture in a user-programmable integrated circuit includes a hard logic block having inputs and outputs, a first group of user-configurable general-purpose routing resources coupled to first selected ones of the inputs of the hard logic block, a soft logic block having inputs and outputs, first selected ones of the inputs of the soft logic block coupled to the first group of user-configurable general-purpose routing resources, first selected ones of the outputs of the soft logic block having dedicated connections to second selected ones of the inputs to the hard logic block, and a second group of user-configurable general-purpose routing resources coupled to second selected ones of the outputs of the soft logic block and to first selected ones of the outputs of the hard logic block.