FPGA Matrix Multiplication for Dynamic System Simulation
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Solution Overview
Problem
Existing methods for simulating dynamic systems, particularly electric circuits, are inefficient due to high latency requirements and complex configuration processes in FPGA devices, which limit the ability to dynamically adjust cycle times or step sizes in simulations.
Innovation Solution
A method utilizing a programmable logic device for parallel multiplication of matrix blocks and sequential processing through an adder tree, with dynamic adjustment of the number of blocks and adder stages based on system equation parameters, allowing for reduced cycle times and efficient simulation of small electric circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a programmable logic device with dynamic configuration is used to reduce latency, then the simulation speed improves, but the configuration complexity and time increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-defining a fixed FPGA configuration that can be loaded once and reused multiple times. This eliminates the need for repeated synthesis and implementation, reducing configuration time from hours to minutes while maintaining the ability to dynamically adjust simulation parameters during operation.
2Loss of time
If matrix multiplication is performed using traditional sequential methods, then the implementation is simpler, but the cycle time increases
Solution Approach 1:
The patent applies segmentation by dividing the matrix multiplication into multiple parallel processing blocks that operate simultaneously on different elements of the matrix. This parallel architecture reduces the overall computation time from O(n) to O(log n) by organizing the calculation into a tree structure where multiple operations occur in each time step.
Solution Approach 2:
The patent transforms the sequential one-dimensional computation into a two-dimensional parallel processing structure by arranging matrix elements in a grid and using both spatial dimensions for simultaneous computation. This dimensional transformation enables multiple multiplication operations to occur in parallel, significantly reducing cycle time.
3Measurement precision
If the FPGA configuration is customized for each simulation scenario, then the measurement precision improves, but the ease of operation decreases
Solution Approach 1:
The patent applies universality by designing a fixed FPGA configuration that can handle multiple simulation scenarios through parameter adjustment rather than reconfiguration. The same hardware structure can simulate different circuit configurations by loading different initial values and parameters, making the system both precise and easy to operate.
Data Source
AI summary
A method for computer-based simulation or control of a dynamic system using a computer includes: cyclically receiving, by a programmable logic device, at least one input signal; calculating, by the programmable logic device, at least one matrix multiplication; and outputting, by the programmable logic device, at least one output signal. A configuration of the programmable logic device includes: a parallel multiplication of blocks of at least two elements of a matrix by at least one input-signal-dependent element of a vector, and an adder tree for multiplication results. Successive blocks of the matrix are temporarily stored in a pipeline and processed sequentially. A target number of blocks and a target adder stage are determined based on a number and/or values of parameters of at least one system equation. Processing of blocks for a current cycle is terminated based on the target number of blocks and the target adder stage being reached.