Fused FPGA Memory-Arithmetic Tile for Higher Bandwidth Logic
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Solution Overview
Problem
The practical size/width of arithmetic logic blocks in FPGAs is limited by the number of available inputs and outputs provided by the routing network, leading to reduced logic density and increased latency when larger operations are attempted through cascading smaller blocks.
Innovation Solution
Fusing memory and arithmetic circuits on a single FPGA tile, allowing direct connections between tiles and utilizing intra-tile communications to increase bandwidth and reduce reliance on the switch fabric, thereby enhancing data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the routing network is used to connect logic blocks, then programmability and flexibility are achieved, but the routing network is less dense and supports less data than arithmetic logic blocks for a given area
Solution Approach 1:
The patent merges memory circuits and arithmetic circuits into a single fused tile structure, allowing direct intra-tile connections between memory outputs and arithmetic logic inputs. This integration eliminates the need for data to traverse the switch fabric routing network, thereby increasing data support capacity while maintaining programmability through configurable logic blocks and routing within the tile.
2Adaptability or versatility
If larger arithmetic operations are achieved by cascading smaller arithmetic logic blocks, then larger operations are enabled, but unnecessary latency is introduced and overall logic density is significantly reduced
Solution Approach 1:
The patent combines multiple arithmetic logic blocks and memory circuits into a single fused tile with direct internal connections. This allows larger arithmetic operations to be performed within the tile using direct wiring rather than cascading through multiple separate blocks via the routing network, thereby reducing latency while maintaining the capability to perform large operations.
Solution Approach 2:
The patent introduces a new dimension of data flow by creating direct intra-tile connection paths that bypass the traditional two-dimensional routing network. This dimensional shortcut allows data to move directly between memory and arithmetic units within the same tile, eliminating the latency associated with traversing the full routing fabric.
3Adaptability or versatility
If larger arithmetic operations are achieved by cascading smaller arithmetic logic blocks, then larger operations are enabled, but overall logic density is significantly reduced
Solution Approach 1:
The patent merges memory circuits and arithmetic circuits into a single fused tile structure, allowing larger arithmetic operations to be implemented within a compact area. By integrating multiple functions (memory, arithmetic logic, and routing) into one tile, the design achieves high logic density while supporting large-scale arithmetic operations that would otherwise require cascading separate blocks across a larger area.
Data Source
AI summary
A tile of an FPGA fuses memory and arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased. The arithmetic unit accesses inputs from a combination of: the switch fabric, the memory circuit, a second memory circuit of the tile, and a cascade input. In some example embodiments, the routing of the connections on the tile is based on post-fabrication configuration. In one configuration, all connections are used by the memory circuit, allowing for higher bandwidth in writing or reading the memory. In another configuration, all connections are used by the arithmetic circuit.