FPGA-Based Memory Array Structure Analysis via Row Aggression Testing
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Solution Overview
Problem
The high cost and complexity of conventional reverse test devices make it difficult to analyze and test the internal structure of integrated circuits (ICs), especially as chip integration increases and critical dimensions decrease, limiting the ability to effectively perform reverse design without expensive and complicated Automatic Test Equipment (ATE) machines.
Innovation Solution
A method and device using a Field Programmable Gate Array (FPGA) platform to develop a customized memory controller and Double Data Rate (DDR) Physical Layer, which writes preset test patterns into a memory array and performs row aggressing tests to determine the target test pattern and array structure, eliminating the need for expensive ATE machines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional reverse test devices (ATE machines) are used to analyze and test the internal structure of integrated circuits, then measurement precision and reliability are improved, but device complexity and cost increase significantly
Solution Approach 1:
The patent creates a virtual model of the memory array structure in the FPGA that replicates the electrical characteristics and behavior of the actual memory array. This virtual copy allows for testing and analysis without requiring complex physical test equipment, thereby maintaining measurement precision while significantly reducing device complexity and cost.
Solution Approach 2:
The FPGA acts as an intermediary device between the test engineer and the memory array under analysis. By implementing a virtual model in the FPGA, it mediates the testing process, allowing standard FPGA development tools to be used instead of complex ATE machines, thus reducing device complexity while preserving measurement capabilities.
2Measurement precision
If conventional reverse test devices (ATE machines) are used to test memory array structures, then measurement precision is improved, but cost increases significantly
Solution Approach 1:
The patent replaces expensive, specialized ATE machines with a relatively inexpensive FPGA device. The FPGA can be programmed with the virtual model and used for testing, providing a cost-effective alternative that maintains measurement precision while dramatically reducing the cost of the testing setup.
Solution Approach 2:
By creating a virtual model in the FPGA that replicates the memory array's electrical behavior, the patent enables accurate testing using standard, inexpensive FPGA development equipment rather than costly specialized test equipment, thus maintaining measurement precision while reducing cost.
3Reliability
If conventional reverse test devices are used, then reliability of reverse design analysis is improved, but ease of operation deteriorates due to complicated operation processes
Solution Approach 1:
The virtual model in the FPGA is designed to automatically perform testing and analysis functions. The FPGA device can autonomously execute test sequences, collect data, and provide analysis results using standard FPGA development tools, eliminating the need for complex manual operation procedures required by conventional ATE machines while maintaining reliable analysis.
Solution Approach 2:
The FPGA platform provides a universal testing environment that can analyze different memory array structures through software configuration rather than requiring specialized hardware setups for each case. This multi-functionality simplifies operation while maintaining reliable analysis across various memory configurations.
Data Source
AI summary
A method and device for testing a memory array structure, and a non-transitory storage medium are provided. The method includes that: respective storage data corresponding to each preset test pattern is written into a to-be-tested memory array, the each preset test pattern being one of preset test patterns in a preset test pattern library; a row aggressing test is repeatedly performed on the to-be-tested memory array until a bit error occurs in the storage data, to obtain row aggressing test times, corresponding to the each preset test pattern, of the to-be-tested memory array, where the bit error characterizes that the storage data has changed; a target preset test pattern corresponding to the to-be-tested memory array is determined from the preset test pattern library based on the row aggressing test times; and an array structure of the to-be-tested memory array is determined based on the target preset test pattern.