FPGA Configuration Memory ECC for Single-Bit Error Correction
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Solution Overview
Problem
Existing FPGA integrated circuits with non-volatile memory lack a method to detect and correct changes in configuration memory cells caused by ionizing radiation or other factors, leading to potential disastrous consequences for the circuit's functionality.
Innovation Solution
Incorporating an ECC generator/checker that generates and stores error-correction data within the non-volatile configuration memory, allowing for integrity checks during boot-up and enabling correction of single-bit errors, with the option to initiate a full reprogramming cycle if multiple errors are detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If non-volatile memory cells are used for FPGA configuration, then configuration data is retained without power, but any single-bit error caused by ionizing radiation or other factors cannot be detected or corrected
Solution Approach 1:
The patent introduces an intermediary ECC (Error Correction Code) system that mediates between the non-volatile configuration memory and the FPGA logic. The ECC generator/checker acts as a mediator that detects and corrects single-bit errors in configuration bits, allowing the system to maintain both non-volatile storage and error correction capability. The ECC syndrome calculation and correction logic serve as the intermediary mechanism that resolves the contradiction between using simple non-volatile memory and achieving reliable error-free operation.
2Reliability
If ECC generator/checker and ECC data memory cells are added to the FPGA configuration memory, then single-bit errors can be detected and corrected, but the device complexity increases
Solution Approach 1:
The patent segments the configuration memory into distinct functional components: configuration data storage cells, ECC data storage cells, and ECC generator/checker logic. This segmentation allows each component to be optimized independently and integrated systematically. The configuration memory is divided into data bits and corresponding ECC bits, with dedicated hardware blocks for ECC generation during programming and ECC checking during operation, making the complexity manageable and modular.
Solution Approach 2:
The ECC data is generated and stored in the ECC data memory cells during the initial programming phase, before the FPGA begins operation. The integrity-check bit is set during factory programming if boot-up checking is desired. This preliminary action ensures that error correction capability is pre-established, and the FPGA can operate with automatic error detection and correction without adding runtime complexity.
3Reliability
If integrity check is performed during boot-up to detect errors, then configuration data integrity is verified, but boot-up time increases
Solution Approach 1:
The patent implements a selective integrity checking approach where the user can choose whether to perform full integrity checks during boot-up by setting the integrity-check bit. This partial action approach allows the system to balance between verification thoroughness and boot-up speed. Additionally, the ECC system is designed to correct single-bit errors automatically without requiring full reprogramming, which would be excessive action and time-consuming.
Data Source
AI summary
A method and apparatus are provided for an error-correcting FPGA. ECC data for configuration is generated and programmed into the ECC rows in the configuration memory. While booting, it is determined whether an integrity-check bit is set. If so, an integrity check is performed. If a single-bit error is detected, if the bit error is an erroneous “0” value, the memory location containing the erroneous “0” value is reprogrammed to a “1” value. If the bit error is an erroneous “1,” value, the memory block data is saved in a non-volatile memory block, the configuration memory block containing the error is erased and reprogrammed using the corrected bit. If there is more than one error, an error flag is set. The user reads the status of the error flag through the JTAG port. If the error flag is set then a full reprogramming cycle is initiated.