FPGA Memory Encoding for Scanner Calibration

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Solution Overview

Problem

Scanner calibration systems, particularly those using Field Programmable Gate Arrays (FPGAs), face challenges due to limited memory capacity, which is a scarce and expensive resource, necessitating improved memory efficiency without compromising performance.

Innovation Solution

The system employs encoding and decoding techniques to reduce memory consumption by converting 10-bit gain and offset values to 9-bit representations, matching the native memory block aspect ratio of FPGAs, thereby reducing memory requirements by 20% without degrading image quality or resolution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If 10-bit gain and offset values are stored in FPGA memory, then calibration precision is maintained, but memory consumption increases

Engineering Contradiction:
Improvecalibration precisionVSAvoidmemory consumption
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent changes the bit-depth parameter of stored calibration data from 10-bit to 9-bit, reducing memory consumption while maintaining adequate calibration precision through selective truncation of least significant bits

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies partial precision by storing only the most significant 9 bits of the 10-bit calibration values, recognizing that full precision is not always necessary for the intended application

Inventive Principle:
Principle #16Partial or excessive action

2Reliability

If memory capacity is increased to store more calibration data, then calibration quality is improved, but system cost increases

Engineering Contradiction:
Improvecalibration qualityVSAvoidsystem cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent modifies the data width parameter from 10-bit to 9-bit for stored calibration values, reducing memory requirements and thereby lowering system cost while preserving sufficient calibration quality

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If 10-bit scan data is processed with 10-bit calibration values, then image quality is maintained, but memory bandwidth requirements increase

Engineering Contradiction:
Improveimage qualityVSAvoidmemory bandwidth requirements
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent reduces the bit-depth parameter of calibration data from 10-bit to 9-bit, decreasing memory bandwidth requirements for data transfer while maintaining adequate image quality through the preserved most significant bits

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11743412B2Reduced memory scanner calibration system and method
Publication Date: 2023.08.29 GENESEE VALLEY INNOVATIONS LLC
  • US11743412B2 patent drawing
  • US11743412B2 patent drawing
  • US11743412B2 patent drawing

AI summary

A scanner calibration system is provided. The scanner calibration system includes memory configured in a format to store therein encoded gain and offset parameters. Such a configuration reduces the amount of required memory for the scanner calibration system without a compromise of performance.