FPGA Configuration Memory Inversion to Mitigate Imprinting
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Solution Overview
Problem
Memory imprinting, or data remanence, occurs in electronic systems where volatile memory cells retain the same values for extended periods, leading to security vulnerabilities as adversaries can extract imprinted values and reverse-engineer executable code, especially in security-critical systems, with previous techniques being either ineffective or costly.
Innovation Solution
A method involving a data inversion scheme and architecture that alternates electrical high and low voltage states for memory cells over the system's lifetime by using a CM input inversion plane, output inversion plane, and an inversion control module to determine operation modes based on cumulative time, ensuring equal exposure to both states, thereby mitigating memory imprinting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If volatile memory cells continuously hold the same data values for extended periods, then memory imprinting occurs and security is compromised, but frequent memory erasure or ping-pong techniques increase system complexity and cost
Solution Approach 1:
The patent implements periodic inversion of data values stored in volatile configuration memory cells. An inversion control module alternates between normal mode and inversion mode, swapping logical 0s and 1s at regular intervals determined by cumulative time tracking. This periodic action prevents memory cells from continuously experiencing the same electrical state, thereby mitigating memory imprinting without requiring complex redundant memory structures
Solution Approach 2:
The system uses its own operational time tracking to automatically determine when inversion should occur. The inversion control module monitors cumulative system time and autonomously switches between normal and inversion modes, eliminating the need for external control mechanisms or complex management systems. The memory system essentially manages its own imprinting prevention through self-monitoring of operational duration
2Reliability
If data values are frequently inverted to prevent memory imprinting, then security is improved, but memory density and operational efficiency decrease
Solution Approach 1:
The patent introduces dynamic mode switching between normal and inversion states based on cumulative time tracking. The system adapts its data storage representation over time, transitioning from static continuous holding of values to dynamic periodic inversion. This dynamic approach maintains security protection while minimizing disruption to normal operations, as the inversion occurs at controlled intervals rather than continuously
Solution Approach 2:
The inversion control module implements feedback by tracking cumulative system time and using this information to determine when inversion should occur. The system monitors its own operational state and adjusts the inversion timing accordingly, ensuring that inversion happens at optimal intervals to prevent imprinting while maintaining operational efficiency. This feedback mechanism prevents both under-inversion (which would fail to protect) and over-inversion (which would reduce efficiency)
3Reliability
If ping-pong techniques with dual registers are used to mitigate imprinting, then memory imprinting is reduced, but memory density and cost increase significantly
Solution Approach 1:
Instead of using dual register structures that duplicate memory resources, the patent inverts the data values within the same memory cells. Rather than creating redundant storage structures, the system achieves imprinting mitigation by swapping the logical representation (0 becomes 1, 1 becomes 0) of the same physical memory contents. This inversion approach provides protection against memory imprinting while maintaining full memory density, avoiding the resource overhead of ping-pong techniques
Data Source
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AI summary
A method and architecture for mitigating configuration memory imprinting in programmable logic devices. At power-up, a configuration memory inversion control determines whether to operate the current power cycle in normal mode or inversion mode, with an objective of equal time in each mode over the system's lifecycle. A configuration memory (CM) input inversion plane is positioned between a CM controller and the CM cells, and a CM output inversion plane is positioned between the CM cells and the FPGA function blocks. When running in inversion mode, data to/from the CM cells is inverted (0's and 1's are swapped) by the input and output inversion planes. By balancing time individual memory addresses spend in high and low voltage states, the system minimizes differences in memory cell stresses, thus reducing memory imprinting effects. The same concept applied to other architectures, such as a processor's external RAM and internal cache, is also disclosed.