FPGA Memory PUF Using LUT Startup States for Low Area Overhead
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Solution Overview
Problem
Current Physical Unclonable Function (PUF) implementations on Field Programmable Gate Arrays (FPGAs) face challenges due to high area overhead, making them costly and resource-intensive, especially for devices with size constraints, and are vulnerable to tampering.
Innovation Solution
A method that utilizes re-configurable logic elements on FPGAs to generate a unique digital fingerprint by programming back-to-back inverters and multiplexers, leveraging the intrinsic variability of memory cells to create a low-area PUF, which combines logic levels to form a signature without additional circuitry, utilizing existing memory elements as a source of entropy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional PUF implementations (such as ring oscillator PUF) are used on FPGA, then unique digital fingerprint generation is achieved, but area overhead becomes large
Solution Approach 1:
The invention utilizes the FPGA's existing memory elements (LUTs and flip-flops) to generate the PUF signature without requiring dedicated PUF circuitry. The memory elements naturally exhibit manufacturing variations that can be exploited for fingerprint generation, allowing the device to serve itself for security functions.
Solution Approach 2:
The patent makes the existing memory elements serve dual purposes: both their intended logic/memory functions and PUF signature generation. By configuring LUTs and flip-flops in specific patterns during initialization, the same hardware resources provide both computational functionality and unique device identification.
2Reliability
If additional PUF circuitry is added to FPGA board, then security primitive is provided, but silicone space is consumed and vulnerability to tampering increases
Solution Approach 1:
The FPGA's existing memory infrastructure is repurposed to provide security primitives. No additional dedicated security circuitry is required because the memory elements themselves can generate unique signatures based on their inherent manufacturing variations.
Solution Approach 2:
The invention extracts the PUF functionality from separate dedicated circuits and integrates it into the existing memory fabric of the FPGA. By taking out the PUF function and embedding it within the memory elements, the design eliminates the need for separate security circuitry.
3Area of stationary object
If shift register-based PUF is implemented using programmable elements, then area overhead is reduced compared to ring oscillator PUF, but resource consumption remains significant for large signatures
Solution Approach 1:
The memory elements (LUTs and flip-flops) are configured to simultaneously serve their logic functions and generate PUF signatures. During initialization, the memory elements naturally settle into states based on manufacturing variations, providing signature bits without requiring dedicated shift register circuits.
Solution Approach 2:
The patent merges the PUF signature generation function with the existing memory element operations. By combining these functions into the same hardware resources, the design achieves both area efficiency and signature generation capability without requiring separate circuit paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces area overhead significantly, allowing for the generation of unique signatures with minimal space usage and enhanced security, as it utilizes existing FPGA resources, making it suitable for devices with area constraints and improving resistance to tampering.
Implementation Method 1
Characteristics, such as the slight variations from the manufacturing process or the power-up state of an SRAM memory cell, can be used to generate a digital fingerprint unique to a single device
Data Source
AI summary
Methods and systems are directed to creating a physical unclonable function (PUF) on a Field Programmable Gate Array (FPGA) and generating a unique signature for a device. The method includes, in part, designing a PUF by taking advantages of programmable logic elements on the FPGA, and extracting uninitialized values associated with one or more storage elements comprised in the PUF when the FPGA is powered up. The extracted uninitialized values can be combined to generate the unique signature for the device. The one or more storage elements can be bi-stable memory cells that are mapped to look up tables (LUTs) on the FPGA. The coordinates of these LUTs can be determined based on hamming distance analysis. Alternatively, the one or more storage elements can be memory cells associated with boundary scan cells of a boundary scan chain.