FPGA Embedded Memory Read Bypass for Faster Full-Width Access
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Solution Overview
Problem
Programmable devices face significant time delays in memory access due to width decoding logic, which is particularly problematic for high-speed applications that require full data width access, and existing solutions complicate the system without adequately addressing access times.
Innovation Solution
Incorporating dedicated read output paths that bypass width decoding logic to directly connect memory arrays to a data bus, allowing for improved memory access speeds, especially during full data width operations, and utilizing additional programmable resources for width conversion when needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If width decoding logic is used to enable configurable data widths, then adaptability is improved, but memory access time increases
Solution Approach 1:
The patent segments the read output path into two separate paths: a dedicated full-width read path that bypasses the width decoding logic, and a configurable read path that goes through the width decoding logic. This segmentation allows full-width reads to occur without the time penalty of width decoding, while still maintaining configurable width capability when needed.
Solution Approach 2:
The patent introduces an intermediary mechanism (the dedicated full-width read output path) that mediates between the memory array and the output register, allowing data to be read at full width without passing through the width decoding logic. This intermediary path resolves the conflict between needing width configuration and maintaining fast access.
2Adaptability or versatility
If width decoding logic is added to support multiple data widths, then device functionality is improved, but device complexity increases
Solution Approach 1:
The patent extracts the full-width read function from the width decoding logic path, creating a separate dedicated path for full-width reads. This removes the unnecessary width decoding overhead from the full-width read operation, simplifying the critical path while maintaining the width decoding capability for other operations.
3Loss of time
If full data width access is prioritized for speed, then memory access time is reduced, but configurability for different data widths is limited
Solution Approach 1:
The patent implements a dynamic read output path selection mechanism that can switch between the dedicated full-width read path and the configurable read path through read output path selection logic. This allows the system to adaptively choose the appropriate path based on the required data width, optimizing both speed and configurability.
Data Source
AI summary
A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read output paths for accessing data at the full data width of the memory array. The dedicated read output paths bypass the width decoding logic and provide data from the memory array directly to a data bus, thereby providing improved memory performance when width decoding is not needed. The memory unit can be incorporated in programmable devices and a programmable device configuration can select either the read bypass paths or the width decoding logic. Hardware applications that require width decoding and improved memory access speed can utilize additional programmable device resources outside the memory unit to register the full width data from the memory unit and convert it to a different data width.