FPGA Memory Control for Semiconductor Test Miniaturization

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing semiconductor test apparatuses face challenges in miniaturization and modulization due to limitations in the number of pins and controllers of FPGAs, difficulty in controlling integrated DRAMs, and increased storage capacity requirements, which hinder efficient memory control and integration.

Innovation Solution

A semiconductor test apparatus integrating failure memory (FM) and buffer memory (BM) blocks into a single chip using an FPGA, with a Ping Pong PHY IP configuration, allowing separate control operations and maximizing external memory use through a control interface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple FPGAs are installed to control modules with different operations, then the control capability is improved, but the device complexity and pin limitations increase

Engineering Contradiction:

Improvecontrol capabilityVSAvoiddevice complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines multiple memory controllers (FM controller and BM controller) into a single FPGA device. This single FPGA integrates the functionality that would traditionally require separate FPGAs, thereby reducing device complexity and pin limitations while maintaining the ability to control both failure memory and buffer memory operations independently through software configuration

Inventive Principle:

Principle #5Merging (Combining)

2Ease of operation

If FMs and BMs are configured as separate FPGAs, then individual control is achieved, but miniaturization and modulization become difficult

Engineering Contradiction:

Improveindividual controlVSAvoidminiaturization

Core Design Contradiction:

Ease of operationVSVolume of moving object

Solution Approach 1:

The patent merges the control functions for FMs and BMs into a single FPGA, enabling miniaturization by reducing the number of separate components. The integrated controller maintains individual control capability through software-based management of different memory operations, allowing both failure memory and buffer memory to be controlled independently within a compact, modular design

Inventive Principle:

Principle #5Merging (Combining)

3Quantity of substance

If the storage capacity of FMs and BMs increases to meet DUT requirements, then the storage capacity is improved, but the number of pins and controllers required increases

Engineering Contradiction:

Improvestorage capacityVSAvoidnumber of pins and controllers

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent implements a universal memory controller within the FPGA that can manage both failure memory and buffer memory operations. This multi-functional controller handles various memory operations (read, write, control signals) for both FM and BM through a single integrated device, thereby supporting increased storage capacity without proportionally increasing the number of pins and controllers required

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12498419B2Semiconductor test apparatus using FPGA and memory control method for semiconductor test

Publication Date: 2025.12.16 YC CORPORATION

AI summary

A semiconductor test apparatus comprises a failure memory (FM) block configured to store failure data generated from a result of testing a semiconductor device, a buffer memory (BM) block to/in which the failure data stored in the FM block is configured to be copied/stored, and a field programmable gate array (FPGA) configured to perform a first control operation to control the FM block and a second control operation to control the BM block.