FPGA Middleware Failover via Dynamic Synchronization

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Solution Overview

Problem

Field-programmable gate array (FPGA) middleware frameworks face challenges in ensuring high availability and quick recovery from software and hardware defects, particularly in critical systems, where unplanned downtime needs to be minimized and real-time synchronization between active and passive frameworks is crucial.

Innovation Solution

A method and system for message-based communication and failure recovery in FPGA middleware frameworks, which involves receiving and re-assembling Internet Protocol fragments with sequence numbers, checking for missing sequences, requesting re-transmissions over TCP channels, and activating passive frameworks upon failover detection to maintain real-time synchronization and minimize downtime.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single active FPGA middleware framework is used for message processing, then the system structure is simple, but the system availability is reduced due to unplanned downtime from software and hardware defects

Engineering Contradiction:

Improvesystem availabilityVSAvoidmiddleware framework structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The system is segmented into multiple independent FPGA middleware frameworks (active and passive) that operate separately but can take over from each other. Each framework maintains its own message processing capability, allowing the passive framework to assume the active role when the active framework fails, thereby improving system availability without requiring a completely redundant complex architecture

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The passive FPGA middleware framework is prepared in advance by maintaining synchronization with the active framework's message queue state. This preliminary action ensures that when failover occurs, the passive framework can immediately continue processing without interruption, eliminating downtime while keeping the overall system structure manageable

Inventive Principle:

Principle #10Preliminary action

2Loss of time

If real-time synchronization is maintained between active and passive FPGA frameworks, then failover recovery time is minimized, but the complexity of maintaining synchronization increases

Engineering Contradiction:

Improvedowntime during failoverVSAvoidsynchronization mechanism

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The active FPGA middleware framework transmits message queue state information (sequence numbers, message fragments) to the passive framework as feedback. This continuous feedback mechanism allows the passive framework to maintain synchronization without complex bidirectional communication, minimizing downtime while keeping the synchronization mechanism relatively simple

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The passive framework maintains a copy of the essential state information (message queue status, sequence numbers) from the active framework. This copying approach allows the passive framework to be ready for immediate takeover without requiring complex real-time synchronization protocols, reducing both downtime and synchronization complexity

Inventive Principle:

Principle #26Copying

3Speed

If UDP protocol is used for message transmission, then transmission speed is high, but reliability is reduced due to missing sequence numbers and fragmented messages

Engineering Contradiction:

Improvemessage transmission speedVSAvoidmessage completeness

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The FPGA middleware framework implements its own reliability mechanisms independent of the UDP protocol's limitations. By adding sequence number tracking and fragment reassembly logic within the framework itself, the system achieves reliable message delivery while maintaining UDP's high transmission speed, without requiring the overhead of TCP

Inventive Principle:

Principle #25Self-service

4Reliability

If TCP channel is used for re-transmission of missing messages, then message reliability is improved, but transmission latency increases

Engineering Contradiction:

Improvemessage delivery reliabilityVSAvoidre-transmission latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary actions by maintaining local state information and sequence number tracking for all transmitted messages. When messages are lost, the system can immediately request re-transmission using the pre-established TCP channel without needing to re-establish connections or perform extensive error checking, thereby improving reliability while minimizing re-transmission latency

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11212218B2Method and system for message based communication and failure recovery for FPGA middleware framework

Publication Date: 2021.12.28 TATA CONSULTANCY SERVICES LTD

AI summary

The disclosure herein describes a method and a system for message based communication and failure recovery for FPGA middleware framework. A combination of FPGA and middleware framework provides a high throughput, low latency messaging and can reduce development time as most of the components can be re-used. Further the message based communication architecture built on a FPGA framework performs middleware activities that would enable reliable communication using TCP/UDP between different platforms regardless of their deployment. The proposed FPGA middleware framework provides for reliable communication of UDP based on TCP as well as failure recovery with minimum latency during a failover of an active FPGA framework during its operation, by using a passive FPGA in real-time and dynamic synchronization with the active FPGA.