FPGA Mixed Protocol Tester Architecture
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Solution Overview
Problem
Conventional automated test equipment (ATE) systems are limited in testing multiple devices under test (DUTs) simultaneously due to processing load on the tester processor and bandwidth constraints, and require fixed protocol hardware bus adapter cards, making it inefficient to test DUTs with different communication protocols.
Innovation Solution
A test architecture where command and test pattern generation is transferred to FPGA devices, and communication protocols are reconfigurable on FPGAs, allowing multiple DUTs to be tested with minimal processing load and without the need for protocol-specific hardware adapter cards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If command and test pattern generation is performed by the tester processor, then the system can control test programs, but the processing load on the tester processor increases and bandwidth requirements increase
Solution Approach 1:
The patent segments the command and test pattern generation function by implementing FPGA-based hardware accelerators that operate independently from the tester processor. Each FPGA block can generate commands and test patterns locally, dividing the overall processing workload across multiple parallel hardware units rather than concentrating it on a single processor, thereby reducing the processing load and increasing test throughput.
Solution Approach 2:
The patent introduces FPGA-based hardware accelerators as intermediary components between the tester processor and the devices under test. These intermediaries handle the computationally intensive tasks of command and test pattern generation, reducing the processing load on the tester processor while maintaining system control and increasing overall productivity.
2Adaptability or versatility
If fixed protocol hardware bus adapter cards are used, then the system can test DUTs with specific protocols, but the adaptability to test different protocols decreases and hardware complexity increases
Solution Approach 1:
The patent implements dynamic protocol support by allowing the same FPGA-based hardware accelerator to be reconfigured for different communication protocols through software programming. Instead of having fixed protocol hardware, the system can dynamically switch between protocols (e.g., PCIe, SATA, SAS, USB) by loading different bitstream configurations onto the FPGA, thereby increasing adaptability while reducing hardware complexity.
Solution Approach 2:
The patent creates a universal testing platform where a single FPGA-based hardware accelerator can perform multiple protocol functions. The same physical hardware can be programmed to support different communication protocols, eliminating the need for separate dedicated hardware cards for each protocol type, thus reducing overall hardware complexity while enhancing protocol flexibility.
3Adaptability or versatility
If multiple protocol-specific hardware adapter cards are maintained, then the system can test various DUTs, but the device complexity and cost increase
Solution Approach 1:
The patent merges multiple protocol-specific hardware adapter card functions into a single FPGA-based hardware accelerator. By combining the capabilities of different protocol cards into one reconfigurable platform, the system reduces hardware complexity and cost while maintaining the ability to test various DUTs with different protocols through software-based configuration.
Data Source
AI summary
Automated test equipment capable of performing a high-speed test of semiconductor devices is presented. The automated test equipment comprises a system controller for controlling a test program, wherein the system controller is coupled to a bus. The tester system further comprises a plurality of modules also coupled to the bus, where each module is operable to test a plurality of DUTs. Each of the modules comprises a tester processor coupled to the bus and a plurality of configurable blocks communicatively coupled to the tester processor. Each of the configurable blocks is operable to communicate with an associated DUT and further operable to be programmed with a communication protocol for communicating test data to and from said associated device under test.