FPGA Deep Learning Model Conversion for Low-Overhead Programming
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Solution Overview
Problem
Deep learning applications face complexity and performance overhead due to intricate software stacks, and existing solutions like ASICs and FPGA devices are either too specific or difficult to program for various deep learning tasks.
Innovation Solution
A method to convert trained deep learning models into design abstraction (DA) code, which configures FPGA devices by defining logic block circuits representing processing steps, allowing for efficient programming and alternate programming modes to accommodate hardware limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a complex hierarchical software stack is used for deep learning applications, then multiple applications and features can be supported, but the system overhead increases and performance deteriorates
Solution Approach 1:
The patent extracts the deep learning model logic from the complex software stack and directly implements it as hardware logic circuits in the FPGA. This extraction eliminates the need for multiple software layers, libraries, and frameworks, thereby reducing software stack complexity while maintaining support for multiple deep learning applications through hardware reconfigurability
Solution Approach 2:
The patent replaces the mechanical/software-based deep learning processing system with a hardware-based FPGA implementation. By substituting software execution with hardware circuit execution, the system eliminates software stack overhead while maintaining application versatility through programmable logic that can be reconfigured for different deep learning models
2Productivity
If ASIC is used to optimize deep learning implementation, then performance is improved, but adaptability to different applications is limited
Solution Approach 1:
The patent employs dynamic reconfigurability of FPGA logic circuits to achieve both high performance and adaptability. The hardware logic can be dynamically reconfigured to match different deep learning model requirements, combining the speed of ASIC with the flexibility of programmable devices, thereby resolving the contradiction between performance optimization and application versatility
3Adaptability or versatility
If FPGA device is used for deep learning applications, then adaptability to different models is improved, but programming complexity increases
Solution Approach 1:
The patent implements a self-service compilation system that automatically converts deep learning models into optimized FPGA logic circuits. This automated compilation process eliminates the need for manual FPGA programming, reducing programming complexity while maintaining full adaptability to different deep learning models through automatic model-to-hardware conversion
4Adaptability or versatility
If deep learning software stack is made deeper to support more features, then application capability is improved, but overhead increases and performance decreases
Solution Approach 1:
The patent extracts the feature processing logic from multiple software layers and implements it directly as hardware logic circuits in the FPGA. This extraction consolidates feature support capabilities into a single hardware layer, eliminating software stack overhead while maintaining comprehensive feature support, thereby improving performance without sacrificing adaptability
Data Source
AI summary
Systems and methods for programming field programmable gate array (FPGA) devices are provided. A trained model for a deep learning process is obtained and converted to design abstraction (DA) code defining logic block circuits for programming an FPGA device. Each of these logic block circuits represents one of a plurality of modules that executes a processing step between different layers of the deep learning process.