FPGA Model Conversion Using Logic Blocks for Deep Learning
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Solution Overview
Problem
Deep learning applications on FPGA devices face complexity and overhead issues due to the need for a hierarchical software stack and limited flexibility in programming, which hinders efficient development and performance.
Innovation Solution
A method to convert trained deep learning models into design abstraction (DA) code, which configures FPGA devices with logic block circuits representing processing steps, allowing for optimized programming and reduced overhead by specifying data flow and identifying duplicate operations for efficient resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a hierarchical software stack is used to support deep learning applications on FPGA devices, then the applications can be implemented with multiple frameworks and libraries, but the complexity of the software stack increases and development time is extended
Solution Approach 1:
The patent extracts the essential deep learning functionality from complex software stacks and implements it directly in hardware logic blocks on the FPGA. By taking out the core processing functions and hardwiring them, the system eliminates the need for complex hierarchical software stacks while maintaining support for multiple deep learning applications.
Solution Approach 2:
The patent replaces the mechanical/software-based deep learning processing system with a hardware-based system using FPGA logic blocks. This substitution eliminates software stack complexity and overhead while preserving adaptability through configurable hardware architecture that can be programmed for different deep learning models and applications.
2Adaptability or versatility
If a complex software stack is used to support multiple deep learning applications, then versatility is improved, but additional overhead accrues and performance is affected
Solution Approach 1:
The patent replaces software-based processing with hardware-based processing using FPGA logic blocks. This substitution eliminates software overhead and improves performance while maintaining versatility through configurable hardware that can be programmed for different deep learning applications without the performance penalty of software stacks.
3Productivity
If ASICs are used to optimize deep learning applications, then performance is improved, but the solution becomes too specific and limited in applicability
Solution Approach 1:
The patent creates a universal FPGA-based platform with configurable logic blocks that can be programmed to perform different deep learning functions. Unlike ASICs that are optimized for a single application, this system provides multi-functionality by allowing the same hardware platform to be reconfigured for various deep learning models and applications while maintaining high performance.
Solution Approach 2:
The patent introduces dynamic reconfigurability to the deep learning processing system through FPGA technology. The logic blocks can be dynamically programmed and reconfigured to adapt to different deep learning applications, combining the performance benefits of ASICs with the flexibility of programmable systems.
4Ease of operation
If FPGA devices are programmed with turn-key solutions, then ease of use is improved, but support for applications is limited similar to ASICs
Solution Approach 1:
The patent creates a universal FPGA platform with configurable logic blocks that can support multiple deep learning applications. The system maintains ease of use through a simplified programming interface while providing broad application support through the configurable hardware architecture that can be programmed for different deep learning models.
Data Source
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AI summary
Systems and methods for programming field programmable gate array (FPGA) devices are provided. A trained model for a deep learning process is obtained and converted to design abstraction (DA) code defining logic block circuits for programming an FPGA device. Each of these logic block circuits represents one of a plurality of modules that executes a processing step between different layers of the deep learning process.