FPGA Resource Control via Multi-Stage Priority Scheduling
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Solution Overview
Problem
Existing FPGA resource control systems fail to simultaneously satisfy abstraction, flexibility, controllability, and fairness when multiple user programs share resources, leading to inefficiencies in resource allocation and usage.
Innovation Solution
A resource control device comprising a controller unit to set FPGA IP core resources, a common unit to create user queues with multiple priorities, and a scheduler unit for multi-stage task scheduling across user queues, ensuring fair and flexible allocation of resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple user programs are simply operated as multiple processes, then the system is simple to implement, but the requirements of abstraction, flexibility, controllability and fairness cannot be satisfied simultaneously
Solution Approach 1:
The scheduling system is segmented into multiple priority levels (first priority, second priority, third priority queues) to differentiate and manage multiple user programs. Each priority queue handles specific types of tasks independently, allowing the system to satisfy multiple requirements (abstraction, flexibility, controllability, fairness) simultaneously while maintaining manageable complexity through structured division.
2Device complexity
If FPGA resources are allocated to multiple users without multi-stage scheduling, then resource allocation is simple, but resource efficiency and fairness deteriorate
Solution Approach 1:
The system implements dynamic resource allocation through multi-stage scheduling where the allocation of FPGA resources changes based on task priority and queue status. The scheduler unit dynamically selects tasks from different priority queues and allocates IP cores accordingly, ensuring that high-priority tasks receive resources first while maintaining overall system efficiency and fairness across multiple users.
3Productivity
If multi-stage scheduling is implemented in user queues and between user queues, then resource allocation fairness and efficiency improve, but system complexity increases
Solution Approach 1:
The complex scheduling problem is segmented into manageable stages: first, tasks are organized into priority queues (segmentation by priority level); second, the scheduler unit processes each queue in sequence (segmentation by processing stage); third, IP core allocation is handled separately from task scheduling (segmentation of allocation functions). This segmentation reduces the overall system complexity while maintaining multi-stage scheduling benefits for fairness and efficiency.
4Adaptability or versatility
If IP core resources are shared among multiple programs without controlled allocation, then flexibility is high, but controllability and fairness deteriorate
Solution Approach 1:
The scheduler unit acts as an intermediary between user programs and IP core resources. It receives task requests from multiple programs, applies fairness and controllability rules through the multi-stage scheduling process, and then allocates IP cores accordingly. This intermediary layer maintains flexibility in resource sharing while ensuring controllability and fairness through structured priority-based allocation.
Data Source
AI summary
A resource control device includes: a controller unit configured to set resources related to IP cores of an FPGA 8 in which a user program executes a task; a common unit configured to create a user queue that is a set of queues having a plurality of priorities for each user program, and store tasks in the user queue; and a scheduler unit configured to select a task to be executed by any one of the IP cores by multi-stage scheduling in the user queue and between the user queues.