FPGA Multiplexer Reconfiguration for Programmable Decoupling Capacitance

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Solution Overview

Problem

Integrated circuits, such as FPGAs, face challenges in efficiently managing decoupling capacitance and resistance in their decoupling capacitance paths, which affects performance and power consumption, as existing methods do not effectively utilize inactive or static multiplexers to optimize these parameters.

Innovation Solution

The method involves programming inactive or unused multiplexers to increase decoupling capacitance and static multiplexers to decrease resistance by selectively connecting inputs with the same data state or polarity to the multiplexer output, thereby incorporating parasitic capacitance into the decoupling path and creating additional circuit paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional decoupling capacitance methods are used, then decoupling capacitance is provided, but inactive multiplexers are wasted and do not contribute to performance optimization

Engineering Contradiction:

Improvedecoupling capacitanceVSAvoidutilization of inactive components

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The inactive multiplexers serve themselves by providing decoupling capacitance through their inherent parasitic capacitance, rather than requiring separate dedicated decoupling components. The multiplexers' own structural characteristics are leveraged to benefit the circuit.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The multiplexers perform dual functions: their primary switching function and an additional decoupling capacitance function. This multi-functionality allows inactive multiplexers to contribute to power integrity without interfering with their designated logic functions.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Use of energy by moving object

If decoupling capacitance path resistance is reduced, then power consumption is improved, but existing methods do not effectively utilize available circuit resources

Engineering Contradiction:

Improvepower consumptionVSAvoiddecoupling capacitance path resistance

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The parasitic capacitance, which is typically considered a harmful or unwanted characteristic in multiplexer design, is converted into a beneficial decoupling capacitance resource. This transforms a negative attribute into a positive contribution to power integrity and energy efficiency.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The invention changes the functional parameter of the multiplexer from purely switching to simultaneously providing capacitance. By programming the multiplexer output to connect to VDD or VSS, the parasitic capacitance parameter is utilized to reduce the overall decoupling path resistance and improve power consumption characteristics.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If programmable logic is configured for optimal performance, then logic functionality is achieved, but unused multiplexers remain inactive and do not contribute to decoupling

Engineering Contradiction:

Improvelogic functionalityVSAvoiddecoupling capacitance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The multiplexer continues to provide useful action even when inactive for its primary switching function. By programming the output to connect to power or ground rails, the multiplexer maintains continuous useful action as a decoupling element, ensuring power integrity throughout the circuit's operation.

Inventive Principle:

Principle #20Continuity of useful action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the decoupling capacitance and reduces the resistance of the decoupling capacitance path, improving the overall performance and power management of integrated circuits by effectively utilizing previously inactive components.

Implementation Method 1

increase decoupling capacitance by incorporating parasitic capacitance(s) of transistors of unused or inactive multiplexers into the decoupling path

Methodology Applied

Scientific EffectParasitic capacitance: Parasitic Capacitance

Implementation Method 2

decrease resistance of the decoupling capacitance path by electrically coupling one or more (or all) unselected inputs of the static multiplexer to the multiplexer output

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS9786361B1Programmable decoupling capacitance of configurable logic circuitry and method of operating same

Publication Date: 2017.10.10 ANALOG DEVICES INC

AI summary

An integrated circuit comprising at least one logic tile including a plurality of multiplexers interconnected into a network configuration, wherein each multiplexer includes a plurality of inputs, an output and a plurality of selection inputs to receive selection signals to determine whether an input of the plurality of inputs is connected to the output. The logic tile further includes (i) at least one inactive multiplexer having an output that is inactive in the network configuration and/or (ii) at least one static multiplexer receiving static selection signals, wherein during operation of the integrated circuit, the selection inputs of the inactive and/or the static multiplexer receive selection signals responsively connect (whether directly or indirectly) two or more inputs of the inactive and/or the static multiplexer to the output of the inactive multiplexer.