FPGA Multiplier LUT6 Layout for Lower Area and Power
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Solution Overview
Problem
Existing FPGA multiplier designs are inefficient in terms of area usage and power consumption, limiting the number of multipliers that can be implemented on a single chip and affecting the performance of neural networks that require numerous multiplication operations.
Innovation Solution
The use of radix-4 modified Booth encoding with novel six-input lookup tables (LUT6s) that allow for efficient sharing of inputs between pairs of LUT6 blocks, reducing the number of logic blocks required for multiplication and enabling more compact implementations, such as supporting both signed and unsigned multiplications without additional logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional FPGA multiplier designs are used, then multiplication functionality is achieved, but area usage is excessive and power consumption is high
Solution Approach 1:
The patent combines multiple functionality into a single logic block. The six-input LUT6 is configured to perform both multiplication and accumulation operations, merging what would traditionally require separate multiplier and adder circuits into one unified block. This merging reduces the total area required and allows more such blocks to be packed on a single chip, directly addressing the contradiction between area efficiency and multiplication capability.
Solution Approach 2:
The logic block designed in the patent is universal, capable of performing multiple functions including multiplication, accumulation, and different types of Booth encoding (radix-4 and radix-8). This multi-functionality means that a single block can replace what would traditionally require multiple specialized blocks, reducing overall area usage while maintaining or enhancing the number of operational units that can be implemented on the chip.
2Use of energy by stationary object
If conventional FPGA multiplier designs are used, then multiplication operations are performed, but power consumption is excessive
Solution Approach 1:
By merging multiplication and accumulation into a single operation within the LUT6-based logic block, the patent reduces the number of separate circuit operations required. This consolidation reduces the total number of active logic elements and interconnections, thereby reducing dynamic power consumption while maintaining the throughput required for neural network training.
Solution Approach 2:
The patent employs different Booth encoding schemes (radix-4 and radix-8) that change the operational parameters of the multiplier. These encoding methods reduce the number of partial products that need to be computed and added, directly reducing the computational complexity and associated power consumption while maintaining multiplication accuracy and speed.
3Productivity
If more multipliers are packed on a single chip, then neural network training rate improves, but area constraints are violated
Solution Approach 1:
The patent merges multiplication and accumulation functions into a single logic block, effectively doubling the functional density per block. This allows twice as many operational units to be packed into the same chip area, directly enabling higher neural network training rates without exceeding area constraints.
Solution Approach 2:
The patent segments the multiplication process into efficient stages using Booth encoding (radix-4 or radix-8), where each stage processes multiple bits simultaneously. This segmentation allows for more compact circuit design with fewer logic blocks required, enabling higher density implementation on the chip.
Data Source
AI summary
In some example embodiments a logical block comprising twelve inputs and two six-input lookup tables (LUTs) is provided, wherein four of the twelve inputs are provided as inputs to both of the six-input lookup tables. This configuration supports efficient field programmable gate array (FPGA) implementation of multipliers. Each six-input LUT comprises two five-input lookup tables (LUT5s) that are used to form Booth encoding multiplier building blocks. The five inputs to each LUT5 are two bits from a multiplier and three Booth-encoded bits from a multiplicand. By assembling building blocks, multipliers of arbitrary size may be formed.