Circuit-Level Signal Assignment for FPGA Multiplier Power Reduction
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Solution Overview
Problem
Conventional techniques for optimizing power usage in integrated circuits, particularly in components like multipliers, are limited, leading to inefficient energy consumption and heat generation, with no established methods for minimizing power usage in field programmable gate arrays (FPGAs).
Innovation Solution
The approach involves circuit-level transformations and assignments that assign frequently toggling signals to lower power inputs, minimize signal changes, and split large multipliers into smaller ones, recombining their results, while using registers to synchronize input changes and reduce power consumption by optimizing port assignments based on toggle rates and signal widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional techniques are used to implement multipliers in FPGA, then the circuit functionality is achieved, but power consumption is high
Solution Approach 1:
The patent segments the multiplier circuit into multiple independent multiplier blocks, each handling a portion of the overall multiplication task. This segmentation allows each block to be optimized independently for power efficiency while maintaining the overall computational functionality, directly addressing the high power consumption issue in conventional FPGA multiplier implementations.
Solution Approach 2:
The patent changes the operational parameters of the multiplier circuits by implementing different assignment strategies for input signals to various ports. By optimizing which input signals are assigned to which ports based on their toggle rates and power consumption characteristics, the patent achieves significant power reduction while maintaining computational accuracy and speed.
2Use of energy by moving object
If signals are assigned to ports without optimization, then circuit implementation is simple, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-analyzing the toggle rates and power consumption characteristics of input signals before assigning them to multiplier ports. This pre-optimization process determines the optimal assignment strategy in advance, reducing power consumption without requiring complex real-time adjustments during circuit operation.
Solution Approach 2:
The patent implements self-service through automated tools that perform the power optimization analysis and signal assignment. The system analyzes circuit characteristics, determines optimal port assignments, and generates the optimized circuit configuration automatically, reducing the manual complexity burden on designers while achieving power efficiency.
3Productivity
If large multipliers are used, then computational capability is high, but power consumption and area increase
Solution Approach 1:
The patent divides large multiplier operations into multiple smaller multiplier blocks that process portions of the input data independently. Each small multiplier consumes less power than a single large multiplier, and their combined output achieves the same computational capability, effectively resolving the trade-off between computational capability and power consumption.
Solution Approach 2:
The patent merges the results from multiple small multiplier blocks to achieve the computational capability of a large multiplier. By combining the outputs of optimized small multipliers with appropriate weighting and summation, the system achieves equivalent computational power with reduced overall power consumption and smaller area utilization.
Data Source
AI summary
Optimizing the power used in an integrated circuit. A circuit-level transformation/permutation reduces the power consumed by multipliers or other components in integrated circuits. Signals that toggle frequently are assigned to lower power multiplier ports or the number of times a signal changes value is minimized. Large width signals are assigned to the low power port. Large multipliers are divided up and optimized as above. Pipelined multipliers are used with registers so that signals change together.