FPGA Netlist Generation via Selective Block Switching
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Solution Overview
Problem
Existing methods for generating netlists for programmable logic devices (PLDs) like FPGAs face challenges in balancing the use of manufacturer-specific code with user-specific code, leading to high resource occupancy, long build times, and limited flexibility, especially in real-time simulation applications where short cycle times and low latencies are critical.
Innovation Solution
A method that involves providing a first PLD code as a netlist, a second PLD code with alternative functional blocks, and a switch PLD code with constant switch driving signals to connect these blocks, allowing for the creation of an overall netlist that optimizes resource usage by removing unused blocks and switches, thereby increasing flexibility and reducing build times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manufacturer-specific PLD code is loaded onto the FPGA to provide fixed functionality, then system reliability and ease of operation are improved, but resource occupancy increases and flexibility decreases
Solution Approach 1:
The manufacturer code is divided into multiple functional blocks, each representing a discrete functionality. These segmented blocks can be independently selected and loaded onto the FPGA based on specific application requirements, allowing the system to maintain reliability through proven manufacturer code while improving flexibility by loading only necessary functions.
Solution Approach 2:
The system transitions from a static, fixed configuration to a dynamic, selectable configuration. The PLD code loading mechanism allows dynamic selection of functional blocks at runtime or compilation time, enabling the FPGA to adapt its resource occupancy based on actual needs while maintaining the reliability benefits of manufacturer-provided code.
2Adaptability or versatility
If complete manufacturer PLD code is loaded onto the FPGA, then functionality completeness is improved, but build time increases
Solution Approach 1:
The unnecessary portions of the manufacturer code are extracted and excluded from the loading process. By analyzing the application requirements and selectively loading only the required functional blocks, the system achieves functionality completeness for the specific application while dramatically reducing build time compared to loading the complete manufacturer code set.
Solution Approach 2:
Instead of loading the complete manufacturer code (excessive action), the system loads only the partial set of functional blocks that are actually required for the specific application. This partial loading approach maintains sufficient functionality completeness while reducing build time proportionally to the amount of code excluded.
3Ease of operation
If FPGA resources are occupied by manufacturer code, then default functionality is ensured, but available resources for user code decrease
Solution Approach 1:
Instead of uniformly occupying FPGA resources with manufacturer code, the system applies local quality by selectively loading manufacturer code only in the specific regions or functional blocks where it is needed. This allows default functionality to be maintained in critical areas while preserving FPGA resources in other areas for user code implementation.
Data Source
AI summary
The present disclosure relates to a method for generating an overall netlist (50) comprising the following steps: providing a first PLD code (24) as first netlist (26), wherein the first PLD code (24) has at least one first functional block (28), providing a second PLD code (30), wherein the second PLD code (30) has at least one second functional block (32) for alternative use instead of a corresponding first functional block (28), providing a switch PLD code (40) having at least one switch (42) assigned to the at least one first functional block (28) for connecting the first functional block (28) assigned to the switch (42), connecting the at least one second functional block (32) to one switch from the at least one switch (42) as an alternative to the corresponding first functional block (28), implementing at least one switch driving signal (44) for the at least one second functional block (32), wherein the at least one switch driving signal (44) is assigned to the corresponding switch (42) for connecting the at least one second functional block (32), creating the overall netlist (50) from the first PLD code (24), the second PLD code (30) and the switch PLD code (40), and removing from the overall netlist (50) functional first blocks (28) which are not utilized on the basis of the switch driving signal (44) of the corresponding switch (42).