Incremental Compilation Netlist Merging for FPGA Design
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Solution Overview
Problem
Existing incremental compilation technologies for FPGA designs face data mismatch issues due to back-annotation and lack of global optimizations, leading to inefficient compilation processes and the need for manual delay budgeting.
Innovation Solution
The method involves partitioning the system into logical sections, generating post-fit and post-synthesis netlists, merging them to form a combined netlist, and performing fitting on this combined netlist to avoid data mismatch and enable global optimizations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If back-annotation is used to preserve placement results in incremental compilation, then compilation time is reduced, but data mismatch occurs causing back-annotated placement to become unusable
Solution Approach 1:
The system is partitioned into multiple logical sections or partitions, with each partition having its own netlist that is independently managed. This segmentation allows incremental compilation to operate on individual partitions without affecting others, eliminating data mismatch while maintaining efficiency.
Solution Approach 2:
Multiple partition netlists are merged to form a combined netlist that integrates results from different partitions. This merging process ensures data consistency across partitions while preserving the benefits of incremental compilation by combining post-fit netlists from set-up compilation with post-synthesis netlists from incremental compilation.
2Productivity
If a bottom-up hierarchical flow is used to develop blocks separately in parallel, then development efficiency is improved, but global optimizations cannot be performed on the blocks
Solution Approach 1:
The patent merges multiple partition netlists into a combined netlist that enables global optimizations while preserving the parallel development benefits of bottom-up flow. The merging process integrates information from all partitions, allowing global optimization algorithms to operate on the complete design.
Solution Approach 2:
The combined netlist serves as an intermediary structure that bridges the gap between independent partition development and global optimization. It consolidates information from all partitions in a format that enables global optimization algorithms to operate effectively while maintaining the efficiency of parallel block development.
3Adaptability or versatility
If manual delay budgeting is performed to facilitate global optimizations between blocks, then global optimization capability is improved, but the process becomes tedious and time consuming
Solution Approach 1:
The system automatically performs delay budgeting and global optimization through the merging process of partition netlists. The combined netlist structure enables automated algorithms to perform delay budgeting without manual intervention, eliminating the tedious and time-consuming nature of manual delay budgeting while maintaining global optimization capability.
Data Source
AI summary
A method for designing a system on a target device includes merging a post-fit netlist for a first partition of the system from a set-up compilation with a post-synthesis netlist for a second partition of the system from an incremental compilation to form a combined netlist. Fitting is performed on the combined netlist.