Deterministic FPGA Resource Scheduling for Multi-Tenant Network Services

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Solution Overview

Problem

Current data centers do not allow reconfigurable hardware, such as FPGAs, to be shared among multiple tenants at runtime, limiting flexible and deterministic resource allocation for network services.

Innovation Solution

A method for deterministically estimating and scheduling FPGA resources based on latency and throughput constraints, using a scheduling algorithm selected from a lookup table, to ensure timely and efficient execution of network services across multiple users.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If FPGA resources are shared among multiple tenants at runtime, then resource utilization and flexibility are improved, but deterministic resource allocation and scheduling become more difficult

Engineering Contradiction:
Improveresource sharing flexibilityVSAvoiddeterministic scheduling
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent segments FPGA resources into multiple slots, where each slot can be independently allocated to different tenants. This segmentation enables multi-tenant sharing while maintaining deterministic scheduling within each slot, resolving the contradiction between flexibility and reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic slot allocation that adapts to changing workload demands while maintaining deterministic timing guarantees. The system can dynamically assign slots to different tenants based on runtime conditions, achieving both flexibility and deterministic scheduling.

Inventive Principle:
Principle #15Dynamics

2Productivity

If complex scheduling algorithms are used to optimize resource allocation, then resource utilization efficiency is improved, but scheduling time and system complexity increase

Engineering Contradiction:
Improveresource utilization efficiencyVSAvoidscheduling time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent performs preliminary estimation of maximum latency for network services before final scheduling. This advance assessment allows the system to quickly determine feasibility and select appropriate scheduling algorithms, reducing overall scheduling time while maintaining efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses a lookup table containing pre-evaluated scheduling algorithm implementations. Instead of evaluating all possible algorithms from scratch, the system selects from pre-computed options, significantly reducing scheduling computation time while maintaining optimal resource allocation.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If strict latency constraints are enforced for network services, then service quality is improved, but resource allocation flexibility and throughput are reduced

Engineering Contradiction:
Improvelatency constraint satisfactionVSAvoidnetwork service throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the parameter representation by using slot-based temporal allocation with predetermined time windows. This parameter transformation allows the system to guarantee latency constraints through fixed time slots while maintaining overall system throughput through efficient slot management and parallel processing.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11973674B2Dynamic and deterministic acceleration of network scheduling for shared FPGAs
Publication Date: 2024.04.30 NOKIA SOLUTIONS & NETWORKS OY
  • US11973674B2 patent drawing
  • US11973674B2 patent drawing
  • US11973674B2 patent drawing

AI summary

A method for allocating resources of a field-programmable gate array (FPGA), the method comprising: deterministically estimating a maximum latency for executing a network service at the FPGA; determining that the maximum latency is less than a threshold latency value associated with the network service; outputting an acknowledgement indicating that the maximum latency is less than or equal to the threshold latency value; receiving confirmation that the FPGA has been selected to execute the network service within a threshold time period; and deterministically scheduling the resources of the FPGA for executing the network service in response to receiving the confirmation within the threshold time period.