FPGA Hardware Fast Path for NFV VM Latency Reduction
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Solution Overview
Problem
Current software and hardware approaches for VM-to-VM forwarding in virtualized environments are inadequate for emerging software-defined network (SDN) and Telco networks, where multi-stage packet processing by different virtual network functions (VNFs) on various operating systems requires reduced latency and efficient hardware-based acceleration.
Innovation Solution
The implementation of a hardware-based fast path using a Field-Programmable Gate Array (FPGA) for direct memory access (DMA) operations between virtual machines (VMs) and virtual network functions (VNFs), bypassing software switches to reduce latency and enable multi-stage Service Function Chaining (SFC) processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If software switches (vSwitch) are used for VM-to-VM forwarding, then flexibility and ease of management are improved, but network communication latency increases
Solution Approach 1:
The system segments network forwarding paths into two types: traditional software-based vSwitch paths for general traffic, and hardware-based fast paths for latency-sensitive traffic. This segmentation allows simultaneous operation of both paths, achieving low latency for specific traffic while maintaining management flexibility through the control plane.
Solution Approach 2:
The patent introduces a network function virtualization layer with hardware acceleration capabilities as an intermediary between VMs and the physical network. This intermediary provides fast path forwarding for time-sensitive traffic while the control plane maintains centralized management, thus resolving the contradiction between speed and controllability.
2Speed
If hardware acceleration is added to reduce latency, then network communication speed is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal hardware acceleration platform that can dynamically provision different types of network functions (firewall, load balancer, router, etc.) through software configuration. This multi-functional approach allows a single hardware platform to serve multiple purposes, reducing overall system complexity while providing fast path capabilities.
Solution Approach 2:
The system employs dynamic resource allocation where hardware acceleration resources are provisioned and de-provisioned based on real-time traffic demands. The fast path is dynamically activated only when needed, allowing the system to adapt its complexity level to match operational requirements rather than maintaining fixed high complexity.
3Adaptability or versatility
If multi-stage packet processing by different VNFs is implemented, then network service functionality is improved, but processing latency increases
Solution Approach 1:
The patent segments the multi-stage packet processing into fast path operations handled by hardware acceleration for latency-sensitive tasks, and slow path operations handled by software for complex processing. This segmentation allows critical path operations to bypass software overhead while non-critical operations use full software processing capability.
Solution Approach 2:
The system maintains continuous fast path processing for latency-sensitive traffic flows through hardware acceleration, ensuring that time-critical network services experience minimal latency. The hardware layer operates continuously to handle time-sensitive packets while software processes less time-critical operations.
Data Source
AI summary
Methods and Apparatus for Multi-Stage VM Virtual Network Function and Virtual Service Function Chain Acceleration for NFV and needs-based hardware acceleration. Compute platform hosting virtualized environments including virtual machines (VMs) running service applications performing network function virtualization (NFV) employ Field Programmable Gate Array (FPGA) to provide a hardware-based fast path for performing VM-to-VM and NFV-to-NFV transfers. The FPGAs, along with associated configuration data are also configured to support dynamic assignment and performance of hardware-acceleration to offload processing tasks from processors in virtualized environments, such as cloud data centers and the like.