FPGA Network-on-Chip Bandwidth Expansion via 3D Stacking
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Solution Overview
Problem
The integration of AI modules within FPGA bare dies is limited by chip structure, transmission bandwidth, and computing efficiency, hindering the achievement of expected performance in artificial intelligence applications.
Innovation Solution
An FPGA device with a network-on-chip (NOC) structure is developed, incorporating hardcore and soft-core IP nodes connected through routing channels, along with a silicon-stacked connection module, to expand transmission bandwidth by forming an NOC network that interconnects nodes and allows for external communication, increasing the number of nodes and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If AI modules are integrated within FPGA bare dies, then computing efficiency is improved, but transmission bandwidth is limited by chip structure
Solution Approach 1:
The patent divides the FPGA chip into multiple die (first FPGA die, second FPGA die, third FPGA die) that can be independently manufactured and then stacked together. Each die contains specific functional modules (AI modules, logic resource modules, memory modules), allowing the system to achieve high computing efficiency on each die while overcoming the transmission bandwidth limitations of individual chips through the stacked architecture.
Solution Approach 2:
The patent transitions from a two-dimensional planar chip structure to a three-dimensional stacked structure by laminating multiple FPGA dies vertically. This dimensional change enables significantly increased transmission bandwidth and node capacity without being constrained by the surface area of individual chips, while maintaining the computing efficiency benefits of integrated AI modules.
2Quantity of substance
If more nodes are added to increase bandwidth, then transmission bandwidth is improved, but device complexity increases
Solution Approach 1:
The patent employs standardized interface modules and routing channel structures that can be replicated across multiple dies. The first interface module, second interface module, and third interface module use consistent designs, and the routing channels follow standardized patterns. This universality allows the system to scale to multiple nodes and increased bandwidth while managing complexity through reuse of proven modular components.
3Productivity
If dedicated AI modules are integrated, then artificial intelligence efficiency is improved, but adaptability is reduced by fixed chip structures
Solution Approach 1:
The patent incorporates logic resource modules that can be dynamically configured and programmed after manufacturing. These logic resource modules allow the FPGA device to adapt to different AI algorithms and workloads by reconfiguring the hardware logic, providing dynamic adaptability while maintaining the high computing efficiency of dedicated AI modules through the stacked architecture.
Data Source
AI summary
The present disclosure discloses an FPGA device for implementing a network-on-chip transmission bandwidth expansion function, and relates to the technical field of FPGAs. When a predefined functional module with built-in hardcore IP nodes is integrated in an FPGA bare die, soft-core IP nodes are configured and formed by using logical resource modules in the FPGA bare die and are connected to the hardcore IP nodes to form an NOC network structure, so as to increase nodes and expand the transmission bandwidth of the predefined functional module. On the other hand, the soft-core IP nodes can be additionally connected to input and output signals in the predefined functional module and also can expand the transmission bandwidth of the predefined functional module.