FPGA NOC Routing Node Scheduling for Priority Port Traffic

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Solution Overview

Problem

Traditional routing node scheduling methods in FPGAs involve a single, loop-based approach that affects service performance by equally processing services from various input ports, leading to inefficiencies.

Innovation Solution

A routing node scheduling method for FPGAs that enables input ports sequentially based on a predetermined scheduling order, with higher importance ports enabled more frequently, and includes a scheduling controller that adjusts this order dynamically based on communication importance and network conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a routing node loops through and processes services from various input ports using a single scheduling method, then the scheduling process is simple to implement, but service performance is affected and transmission efficiency is reduced

Engineering Contradiction:
Improvescheduling implementation simplicityVSAvoidservice transmission efficiency
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent implements dynamic scheduling by enabling different input ports at different time points within a scheduling cycle based on communication importance. The scheduling controller dynamically selects which input port to enable at each time point, transitioning from a static loop-based approach to a dynamic priority-based approach. This resolves the contradiction by maintaining implementation simplicity through a systematic enabling sequence while dramatically improving transmission efficiency through priority-based selection.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the scheduling parameter from equal-time allocation to variable-time allocation based on communication importance. Input ports with higher communication importance are enabled for longer durations or more frequently within the scheduling cycle. This parameter change allows the system to maintain simple controller logic while achieving superior service performance by allocating transmission opportunities according to priority levels.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If all input ports are enabled equally in each scheduling cycle, then fairness is maintained among all services, but high-priority services experience delays and overall performance deteriorates

Engineering Contradiction:
Improveservice fairnessVSAvoidhigh-priority service latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies local quality by differentiating the scheduling treatment of different input ports based on their communication importance. Instead of uniform enabling, each input port receives customized enabling duration and frequency according to its priority level. High-priority ports are enabled more frequently and for longer durations, while lower-priority ports receive residual time slots. This resolves the contradiction by maintaining a form of fairness through systematic allocation while prioritizing critical services.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements periodic scheduling cycles where input ports are enabled in a repeating pattern based on their priority levels. Within each scheduling cycle, high-priority input ports are enabled at specific time points with greater frequency, creating a periodic structure that guarantees both fairness (all ports get scheduled) and priority handling (important ports get more opportunities). This periodic approach balances fairness and latency requirements effectively.

Inventive Principle:
Principle #19Periodic action

3Stability of the object's composition

If a fixed scheduling order is used for input ports, then the scheduling process is deterministic and easy to control, but adaptability to changing network conditions is reduced

Engineering Contradiction:
Improvescheduling order stabilityVSAvoidnetwork condition adaptability
Core Design Contradiction:
Stability of the object's compositionVSAdaptability or versatility

Solution Approach 1:

The patent introduces dynamics into the scheduling system by allowing the scheduling order to be adjusted based on real-time communication importance metrics. While the basic enabling sequence remains deterministic for stability, the specific allocation of time slots and enabling durations adapts to changing network conditions. This dynamic adjustment mechanism resolves the contradiction by maintaining controllability through systematic scheduling while achieving adaptability through priority-based reconfiguration.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12542748B2Routing node scheduling method for network on chip (NOC) in field programmable gate array (FPGA)
Publication Date: 2026.02.03 WUXI ESIONTECH CO LTD
  • US12542748B2 patent drawing
  • US12542748B2 patent drawing

AI summary

A routing node scheduling method for an NOC in an FPGA is used when a plurality of input ports each have a data packet to be transmitted to a routing node at the same time. A scheduling controller within the routing node is used to enable each input port according to a predetermined scheduling order, and the routing node receives a data packet through the enabled input port. In addition, quantities of times at least two input ports are enabled are different in one scheduling cycle, which means that the scheduling controller implements biased scheduling control over each input port, allowing different input ports to transmit data packets at different frequencies. This can increase a quantity of times an input port with high communication importance is enabled, making a data packet at the input port be transmitted more timely and achieving better transmission efficiency. The scheduling method can well match transmission requirements of different services to achieve optimal transmission performance of an NOC.