FPGA Non-Volatile Memory Array Drain-Side Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing FPGA devices using Flash memory for programming face inefficiencies in memory cell segmentation, leading to issues with voltage distribution and disturb mechanisms, which affect programming reliability and metal resource utilization.
Innovation Solution
The proposed solution involves a non-volatile memory array with drain-side segmentation, where neighboring memory transistors share common column lines and high-voltage driver transistors, reducing the number of rows exposed to programming voltage and optimizing metal usage through local source biasing and segment-select transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory array is divided into segments with separate source-column lines for each segment, then programming reliability is improved through reduced disturb conditions, but device complexity increases due to additional segment source-column lines and source-segment select transistors
Solution Approach 1:
The memory array is divided into multiple segments along the row direction, with each segment having its own dedicated source-column line. This segmentation isolates programming operations to specific regions, reducing voltage-induced disturb conditions in adjacent memory cells and improving programming reliability.
Solution Approach 2:
A single global read line controls all source-segment select transistors across different segments, enabling universal control functionality. This multi-functionality allows the same control signal to manage multiple segments simultaneously, reducing the need for separate control circuits for each segment and thereby reducing overall device complexity.
2Area of stationary object
If common source lines run the entire length of every column, then metal area requirements are reduced, but voltage distribution efficiency decreases leading to increased disturb conditions
Solution Approach 1:
The source line structure is segmented into multiple independent source-column lines, each serving a specific segment. This segmentation limits the propagation of programming voltage to only the intended segment, improving voltage distribution efficiency and reducing disturb conditions, while the optimized routing minimizes overall metal area usage.
3Reliability
If drain-side segmentation is implemented with segment select transistors, then disturb conditions are minimized through localized voltage control, but manufacturing complexity increases due to additional transistors and interconnections
Solution Approach 1:
The memory array is segmented in the row direction with each segment having dedicated source-column lines and segment select transistors. This segmentation localizes voltage control to specific regions, minimizing disturb conditions and improving programming reliability through precise spatial control of programming operations.
Solution Approach 2:
The segment source-column lines and segment select transistors are designed with universal control characteristics, allowing the same circuit architecture to be replicated across multiple segments. This modular universal design simplifies manufacturing by enabling standardized production processes and reducing the complexity of integrating multiple different circuit types.
Data Source
AI summary
A non-volatile memory array for an FPGA comprises a plurality of memory cells arranged in rows and columns and divided into a plurality of row segments. The source of each non-volatile memory transistor in each segment is coupled together to a common source line. A column segment line is associated with each segment of the array, and is coupled to the drains of each non-volatile memory transistor in the segment. A segment select transistor is coupled between each column segment line and its associated column line, and a high-voltage driver transistor is coupled to each column line.