FPGA Logic Drive Using NVM Cells to Reduce NRE Costs

The patent divides the FPGA chip into multiple logic blocks, each containing lookup tables (LUTs) and flip-flops, that can be independently programmed and configured. This segmentation allows the chip to be divided into functional units that can be selectively activated, reducing the effective area needed for specific applications while maintaining overall adaptability.

The patent implements universal logic blocks that can be programmed to perform multiple different logic functions through configuration memory. Each logic block contains lookup tables that can be programmed to implement any combinational logic function, making the same physical hardware structure capable of multiple functions, thereby reducing the chip area needed compared to having dedicated hardware for each function.

The patent employs dynamic reconfiguration capability where the logic blocks and interconnect structures can be programmed and reprogrammed at runtime to adapt to different computational tasks. This dynamic nature allows the system to optimize power consumption by activating only the necessary logic blocks for a given task, rather than maintaining all possible functions active simultaneously.

The patent implements local interconnect structures that allow signals to be routed only to the specific logic blocks that need them, rather than providing global connectivity to all blocks. This local quality approach reduces the number of active interconnect lines and associated switching elements, thereby reducing overall power consumption while maintaining the ability to reconfigure for different functions.

The patent uses configuration memory (such as SRAM or non-volatile memory) to store the programming data that defines the logic function of each block. This copying approach allows the same physical chip design to be programmed with different logic configurations without requiring different physical masks or fabrication processes, significantly reducing the cost of producing adaptable hardware compared to custom ASIC designs.

The patent changes the functional parameters of the logic blocks through electrical programming of configuration memory cells, rather than changing the physical structure through different fabrication processes. This parameter change approach allows a single fabrication process to produce chips that can be configured for different applications, avoiding the high costs of multiple fabrication runs or custom mask sets required for ASIC production.

The patent creates a universal platform using advanced technology node FPGA chips that can be programmed to implement multiple different applications and algorithms. This universality allows the high NRE cost of the advanced technology node to be amortized across many different product applications, making the high-performance chip economically viable by sharing the fabrication cost across diverse uses rather than requiring separate custom designs for each application.

The patent leverages the high-performance characteristics of advanced technology nodes (such as smaller transistor sizes and higher switching speeds) while using programmable logic to adapt the performance parameters to match specific application requirements. This allows the system to achieve high performance when needed while avoiding the NRE cost of designing and fabricating multiple different high-performance ASICs for different applications, as a single reconfigurable chip can serve multiple performance needs.