Multichip FPGA-NVM Package Layout to Cut Size and NRE Cost

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Solution Overview

Problem

The switch from Field Programmable Gate Array (FPGA) IC chips to Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips is hindered by larger semiconductor chip size, lower fabrication yield, higher power consumption, and increased Non-Recurring Engineering (NRE) costs, which slow down innovation and implementation of advanced semiconductor technology generations.

Innovation Solution

A chip package design incorporating a ball-grid-array (BGA) substrate with metal bumps and a combination of FPGA and non-volatile memory (NVM) IC chips, allowing for efficient signal transmission and power delivery through wirebonded wires and metal bumps, reducing the need for costly ASIC or COT designs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If FPGA IC chip is used for a given application, then adaptability and ease of operation are improved, but semiconductor chip size increases, fabrication yield decreases, and fabrication cost increases

Engineering Contradiction:

ImproveadaptabilityVSAvoidfabrication yield

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The invention divides the system into two separate IC chips: an FPGA chip for programmable logic functions and an ASIC chip for fixed-function high-performance operations. This segmentation allows each chip to be optimized independently - the FPGA chip maintains adaptability while the ASIC chip achieves high fabrication yield and low cost for specific functions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The FPGA chip serves as a universal platform that can be reconfigured for different applications and functions, while the ASIC chip provides specialized functions. Together, they create a multi-functional system where the FPGA handles variable requirements and the ASIC handles fixed, high-performance requirements.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If FPGA IC chip is used for a given application, then adaptability is improved, but power consumption increases

Engineering Contradiction:

ImproveadaptabilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

By separating functions into FPGA and ASIC chips, the system assigns power-intensive fixed functions to the ASIC chip which is optimized for efficiency, while the FPGA chip handles only the adaptable, lower-power control and configuration functions.

Inventive Principle:

Principle #1Segmentation

3Productivity

If ASIC or COT chip is used to expand application volume, then performance is improved, but Non-Recurring Engineering cost increases greatly

Engineering Contradiction:

ImproveperformanceVSAvoidNon-Recurring Engineering cost

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

The invention separates the system into a reusable FPGA platform (avoiding NRE costs) and a dedicated ASIC component only for functions where high performance justifies the investment. This allows most applications to use the cost-effective FPGA while still achieving ASIC-level performance for critical functions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The FPGA chip serves as a cost-effective, reconfigurable alternative to expensive ASIC development, allowing rapid prototyping and deployment without the millions of dollars in NRE costs associated with ASIC design and fabrication.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design reduces semiconductor chip size, lowers fabrication costs, and maintains performance while enabling continued innovation in advanced technology generations, overcoming the limitations of FPGA IC chips.

Implementation Method 1

a first metal bump at a bottom of the ball-grid-array (BGA) substrate, wherein the first metal bump comprises tin

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

allowing for efficient signal transmission and power delivery through wirebonded wires and metal bumps

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS20250336907A1Field programmable multichip package comprising FPGA IC chip and NVM IC chip

Publication Date: 2025.10.30 ICOMETRUE CO LTD

AI summary

A chip package includes a ball-grid-array (BGA) substrate; a first metal bump at a bottom of the ball-grid-array (BGA) substrate, wherein the first metal bump comprises tin; a field programmable chip package over and coupling to the ball-grid-array (BGA) substrate, wherein the field programmable chip package comprises a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip therein and a second metal bump at a bottom of the field programmable chip package and bonded to a top of the ball-grid-array (BGA) substrate; and a memory chip package under and coupling to the ball-grid-array (BGA) substrate, wherein the memory chip package comprises a first non-volatile memory (NVM) integrated-circuit (IC) chip therein and a third metal bump at a top of the memory chip package and bonded to the bottom of the ball-grid-array (BGA) substrate.