FPGA NVMe RAID Accelerator Single PCIe Endpoint Latency

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Solution Overview

Problem

Current information handling systems face latency issues in NVMe RAID stacks due to the increased latency caused by using multiple PCIe endpoints for targeting different drives during I/O operations.

Innovation Solution

An information handling system that uses a single PCIe endpoint to advertise multiple queues, with a Field Programmable Gate Array (FPGA) performing queue-level logical separation to ensure that commands are correctly routed to the intended drives, acting as an intelligent router to reduce latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple PCIe endpoints are used to target different drives, then drive targeting capability is improved, but latency increases

Engineering Contradiction:

Improvedrive targeting capabilityVSAvoidlatency

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent merges multiple PCIe endpoint functions into a single PCIe endpoint by implementing a virtualization layer that allows one endpoint to present multiple queue namespaces to the host. This consolidation maintains the ability to target multiple drives while reducing the overhead associated with multiple endpoint contexts, thereby lowering latency.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces an intermediary layer (virtualization software or firmware) that sits between the host and the physical PCIe endpoints. This intermediary manages queue namespace mappings and command routing, allowing the system to maintain multiple drive targeting capabilities through a single endpoint interface while optimizing command distribution to reduce latency.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Speed

If a single PCIe endpoint is used to reduce latency, then I/O operation speed is improved, but command routing complexity increases

Engineering Contradiction:

ImproveI/O operation speedVSAvoidcommand routing complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent segments the command routing function into distinct queue namespaces, where each namespace corresponds to a specific drive or set of drives. This segmentation allows the single PCIe endpoint to maintain organized, manageable routing tables and mapping structures, reducing the complexity burden while enabling fast I/O operations through optimized namespace-based command distribution.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action by pre-configuring queue namespace mappings and routing tables before I/O operations begin. This pre-establishment of command routing paths eliminates the need for complex real-time routing decisions, thereby maintaining low latency while managing routing complexity through advance preparation of mapping structures.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10628342B1System and method for accelerating performance of non-volatile memory RAID stacks

Publication Date: 2020.04.21 DELL PROD LP

AI summary

An information handling system includes an accelerator that advertises, via a single peripheral component interconnect express endpoint, to a processor a plurality of queues from different drives. The processor writes commands and maps each command to target a particular one of the queues. The accelerator performs a queue level logical separation for the mapped command to be processed by the target queue.