Programmable Logic Device On-Chip Non-Volatile Memory Random Access
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Solution Overview
Problem
Existing non-volatile FPGA devices with on-chip memory are slower in power-on speed due to the need to load configuration data from external sources, and prior art methods for accessing non-volatile memory are limited by line-by-line data transfer, restricting data flexibility and increasing design complexity and cost.
Innovation Solution
A programmable logic device with on-chip user non-volatile memory featuring a SRAM array for real-time configuration, a non-volatile memory block with a single interface for random access, and a programming controller for direct user logic access, enabling flexible data storage and reduced design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If configuration data is loaded from external sources in non-volatile FPGA, then the device can maintain non-volatility, but power-on speed decreases
Solution Approach 1:
Configuration data is pre-loaded into the non-volatile memory block before the device is powered off. When the device is powered on, the configuration data is already available in the on-chip non-volatile memory, eliminating the need to load from external sources and thus improving power-on speed while maintaining non-volatility
2Adaptability or versatility
If line-by-line data transfer method is used for non-volatile memory access, then data can be stored, but data flexibility decreases and design complexity increases
Solution Approach 1:
A memory interface block is introduced as an intermediary between the user logic and the non-volatile memory block. This interface block handles the complex data transfer operations and provides simplified random access functionality to the user, thereby increasing data flexibility while reducing the complexity visible to the user design
Solution Approach 2:
The memory interface block provides multiple functions including random access, data transfer, and interface management, allowing the non-volatile memory to be accessed in various ways (random access, line-by-line) depending on the application needs, thus increasing data flexibility without proportionally increasing design complexity
Data Source
AI summary
The present invention discloses a programmable logic device with on-chip user non-volatile memory, comprising: a programmable logic array, which is a user programmable logic array and comprises a SRAM array and a logic block array with an interface; the SRAM array is used to store configuration data to control the logic block array in real time, therefore, the logic block can be formed to perform the function a user desires; a non-volatile memory block, comprising one or more segments storing configuration data and one or more segments storing user data which is used during FPGA's normal operation after configuration; the non-volatile memory block has only one interface, and the non-volatile memory block connects to a programming controller through the interface; a programming controller, which can randomly access the non-volatile memory through a data bus, an address bus, and corresponding control signals.