Configurable Output Driver Slew Rate Control for FPGA I/O
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Solution Overview
Problem
FPGA devices face compatibility issues due to fixed slew rates, which can cause logic upsets in systems with different I/O signal switching speeds and operating voltages, leading to increased costs from manufacturing multiple versions for various applications.
Innovation Solution
A configurable output driver circuit with pre-driver circuits that adjust the slew rate of output signals by controlling series resistance in PMOS and NMOS transistors, allowing the same FPGA device to operate with different specified slew rates and voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the FPGA output driver operates at high switching speeds to meet high bandwidth requirements, then data transfer performance is improved, but logic upset occurs in systems with slower I/O components
Solution Approach 1:
The patent implements dynamic slew rate adjustment by providing multiple pre-driver circuits with different series resistance values that can be selectively activated based on the target system's speed requirements. This allows the output driver to adapt its switching speed dynamically rather than operating at a fixed high speed, preventing logic upset in slower systems while maintaining high performance capability when needed.
2Adaptability or versatility
If different versions of FPGA devices are manufactured with different output driver slew rates, then compatibility with various IC devices is improved, but manufacturing cost increases and economies of scale are reduced
Solution Approach 1:
The patent makes a single FPGA device version universal by incorporating multiple pre-driver circuits that can be selectively enabled through configuration bits. This single device version can interface with both fast and slow IC devices by activating the appropriate pre-driver circuit, eliminating the need to manufacture multiple specialized versions and thereby maintaining economies of scale while achieving broad compatibility.
3Reliability
If the operating voltage of the FPGA device is increased to comply with certain I/O standards, then voltage compatibility is improved, but the slew rate of output signals changes undesirably
Solution Approach 1:
The patent compensates for unwanted slew rate changes caused by voltage adjustments by providing multiple pre-driver circuits with different series resistance values. When the operating voltage is changed to comply with specific I/O standards, the appropriate pre-driver circuit can be selected to adjust the slew rate back to the desired value, thereby decoupling voltage compatibility from slew rate control.
4Speed
If the slew rate of the output driver is increased to reduce propagation delay, then operating frequency is improved, but noise is introduced into the output signal
Solution Approach 1:
The patent implements dynamic slew rate optimization by providing multiple pre-driver circuits with different series resistance values that can be selectively activated based on the specific application's noise sensitivity and speed requirements. This allows the system to use faster pre-drivers when noise immunity is not critical and slower pre-drivers when minimal noise is required, optimizing the trade-off between propagation delay and noise generation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables compatibility with various IC devices by dynamically adjusting the slew rate of output signals, reducing the need for multiple FPGA versions and maintaining specified signal characteristics across different applications.
Implementation Method 1
The first pre-driver circuit selectively adjusts a series resistance between the PMOS output transistor's gate and ground potential in response to the mode control signal, thereby adjusting the turn-on speed of the PMOS output transistor. The second pre-driver circuit selectively adjusts a series resistance between the NMOS output transistor's gate and the supply voltage in response to the mode control signal, thereby adjusting the turn-on speed of the NMOS output transistor.
Data Source
AI summary
An output circuit allows the slew rate of its output signal to be selectively adjusted. The output driver circuit includes an output driver and pre-driver circuits. The output driver includes an output transistor coupled between a first supply voltage and the output terminal. The pre-driver circuit selectively adjusts a series resistance between the output transistor's gate and a second supply voltage in response to mode control signals.