FPGA Overclocking Control Using Circuit Delay Measurement
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Solution Overview
Problem
Existing methods for handling timing errors in FPGA-based neural network accelerators, such as the ABFT method, are limited to convolution calculations, and timing error warning/delay measurement methods cannot be applied to all timing paths.
Innovation Solution
An automatic overclocking controller using a CPU, clock generator, and timing delay monitor (TDM) controller, which employs two-dimensional multi-frame fusion (2D-MFF) technology to process sampling results, allowing for the detection of transition points and calculation of circuit delay to determine a safe operating frequency for the accelerator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If overclocking technology is used to remove overly conservative time margin, then performance is maximized, but timing error may occur
Solution Approach 1:
The system dynamically changes the clock frequency parameter based on measured timing delays. By continuously measuring the actual delay of critical paths and adjusting the operating frequency accordingly, the system removes the overly conservative time margin while maintaining reliability through real-time parameter adaptation.
Solution Approach 2:
The patent replaces static timing analysis with dynamic measurement-based timing control. Instead of using fixed worst-case margins determined by static analysis tools, the system uses real-time delay measurement and feedback control to dynamically adjust timing parameters, substituting mechanical conservative design with intelligent adaptive control.
2Reliability
If ABFT method is used to verify input and output, then timing error can be detected in convolution calculation, but it cannot be applied to other operators in the neural network
Solution Approach 1:
The patent creates a universal timing error detection mechanism that works across all neural network operators, not just convolution. By using delay measurement at the clocking boundary that is applicable to any operator type (convolution, pooling, activation functions, etc.), the system achieves multi-functionality and broad applicability throughout the entire neural network pipeline.
3Adaptability or versatility
If method based on timing error warning/delay measurement is used, then it can be applied to any operator, but timing detector cannot be applied to all timing paths
Solution Approach 1:
The patent introduces an intermediary delay measurement mechanism that bridges the gap between different timing paths. By placing delay measurement logic at the clocking boundary between pipeline stages, the system creates a universal measurement point that can capture timing information from all timing paths converging at that boundary, enabling comprehensive timing path coverage.
4Reliability
If static timing analysis tool reserves certain timing margin, then worst working condition is covered, but overly conservative time margin reduces performance
Solution Approach 1:
The system performs self-measurement of its own timing characteristics and self-adjustment of operating parameters. By using on-chip delay measurement logic that monitors actual signal propagation delays and feeds this information back to adjust the operating frequency, the system eliminates the need for external conservative timing margins while maintaining reliability through self-service measurement and control.
Data Source
AI summary
An automatic overclocking controller based on circuit delay measurement is provided, including a central processing unit (CPU), a clock generator, and a timing delay monitor (TDM) controller. Compared with the prior art, the present disclosure has following innovative points: A two-dimension-multi-frame fusion (2D-MFF) technology is used to process a sampling result, to eliminate sampling noise, and an automatic overclocking controller running on a heterogeneous field programmable gate array (FPGA) can automatically search for a highest frequency at which an accelerator can operate safely.