FPGA Network Interface for High-Speed Packet Replay
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Solution Overview
Problem
Conventional computing devices are inadequate for high-speed and precise capture and replay of data packets due to internal bottlenecks, such as data transfer limitations and delays from long-term storage to RAM or network interfaces, making it challenging to simulate realistic workloads for debugging network issues.
Innovation Solution
A customized computing device with non-volatile memory for storing data packets, volatile memory for a shared producer queue, and an FPGA-based network interface that reads, rewrites network addresses, generates checksums, and transmits data packets at high speeds, enabling precise replay with adjustable timing and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If off-the-shelf computing devices are used for packet replay, then device complexity is reduced, but replay speed and timing precision deteriorate due to internal bottlenecks
Solution Approach 1:
The system segments the replay functionality into a dedicated network interface card (NIC) with specialized hardware components. The NIC includes separate units for packet storage, processing, address rewriting, and transmission, allowing each component to operate independently at optimal speeds without the bottlenecks of general-purpose computing devices.
Solution Approach 2:
A shared memory queue acts as an intermediary between the packet source and the replay transmission. This shared queue decouples the storage and processing functions from the transmission function, allowing packets to be prepared in advance and transmitted at precise timings without waiting for processing delays.
2Ease of operation
If off-the-shelf computing devices are used for packet replay, then ease of operation is improved, but timing precision deteriorates due to delays from locks and semaphores
Solution Approach 1:
The shared memory queue serves as an intermediary that eliminates the need for locks and semaphores between packet storage and transmission. Multiple processor cores can read from and write to the shared queue simultaneously without contention, ensuring precise inter-packet timing is maintained while allowing parallel processing for ease of operation.
3Adaptability or versatility
If general purpose computers are used for capture, then adaptability is improved, but capture and replay speed deteriorate due to data transfer bottlenecks
Solution Approach 1:
The system segments capture and replay functions into dedicated hardware components within the NIC. Separate storage units, processing units, and transmission units operate in parallel, eliminating the data transfer bottlenecks between storage, RAM, and network interfaces that plague general-purpose computers.
Solution Approach 2:
The patent replaces the mechanical data transfer process of general-purpose computers (storage to RAM to network interface) with a direct memory-to-transmission pipeline in the dedicated NIC. Data flows directly from packet storage through processing to transmission without intermediate transfers, achieving line-speed capture and replay.
Data Source
AI summary
An embodiment may involve non-volatile memory configured to store chunks of data packets, wherein the chunks are associated with sequence numbers; a shared producer queue; one or more processors configured to transfer the chunks to the shared producer queue in order of the sequence numbers; an array of n sets of processors configured to: (i) read the chunks from the shared producer queue, (ii) re-write network addresses within the data packets to create modified chunks, and (iii) write the modified chunks to queues; and a field programmable gate array based network interface containing the queues and m physical ports, and configured to: (i) read the modified chunks in order of their sequence numbers, (ii) unpack the modified chunks into data packets, (iii) write updated checksums to the data packets, (iv) respectively select output ports for the data packets, and (v) transmit the data packets from the selected output ports.