FPGA Packing via Rent Characteristic Optimization
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Solution Overview
Problem
Existing packing algorithms for cluster-based FPGA architectures face challenges in optimizing routability due to sub-optimal Rent characteristics, leading to increased routing requirements and potential degradation of the final solution quality, especially when dealing with complex designs and constraints such as input bandwidth and flip-flop control constraints.
Innovation Solution
A partitioning-based packing approach using recursive bipartitioning to improve the Rent characteristic of the cluster-level netlist, where the process translates the netlist into a hypergraph, partitions it, and adjusts clusters to meet design constraints, focusing on minimizing external nets and optimizing the Rent characteristic, rather than minimizing cuts, to enhance routability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If seed-based packing algorithms are used, then the packing process is simpler to implement, but the Rent characteristic is sub-optimal leading to increased routing requirements
Solution Approach 1:
The patent applies segmentation by dividing the netlist into multiple partitions through recursive bipartitioning before packing into clusters. This pre-segmentation optimizes the Rent characteristic by ensuring that partitions have balanced connectivity properties, which reduces the number of external nets that need to be routed between clusters, thereby reducing overall routing requirements while maintaining implementation feasibility.
Solution Approach 2:
The patent performs preliminary action by conducting recursive bipartitioning of the netlist before the actual packing step. This preliminary partitioning optimizes the Rent characteristic in advance, creating a structured division of logic elements that facilitates more efficient routing in subsequent steps, thus reducing routing requirements before the packing process even begins.
2Productivity
If direct k-way partitioning is used, then the partitioning process is faster, but it is more disruptive to initial partitions reducing solution quality
Solution Approach 1:
The patent applies dynamics by using recursive bipartitioning that dynamically adjusts the partitioning process based on the Rent characteristic optimization goals. Rather than applying a fixed aggressive k-way partitioning, the method adaptively refines partitions through multiple levels of bipartitioning, allowing the process to maintain solution quality while achieving computational efficiency through the recursive nature of the algorithm.
Solution Approach 2:
The patent changes parameters by optimizing for Rent characteristic rather than simply minimizing cuts. This parameter change in the optimization objective leads to partitions that are less disruptive to initial groupings while maintaining partitioning speed, as the Rent-based optimization naturally preserves meaningful connections between logic elements that should remain together.
3Device complexity
If packing optimizes for minimal cuts, then the number of partitions is reduced, but the Rent characteristic is not optimized leading to poor routability
Solution Approach 1:
The patent applies inversion by reversing the traditional optimization objective. Instead of minimizing cuts as the primary goal, the method optimizes for Rent characteristic, which inverts the traditional approach and leads to better routability. This inversion reveals that minimizing cuts alone is insufficient and that Rent-based optimization provides a more comprehensive measure for achieving good routing properties.
Data Source
AI summary
A method for programming a cluster-based field programmable gate array (FPGA) device includes providing a netlist and cluster size information, translating the netlist into a hypergraph, partitioning the hypergraph into multiple partitions and optimizing the Rent characteristic, translating the partitions into clusters, placing the clusters on the FPGA device, routing interconnects using a pre-fabricated routing resource on the FPGA device, generating a programming bitstream in response to the placing and routing, and providing the programming bitstream to the FPGA device to realize the user design.


