Parallel Partial Reconfiguration for FPGA Switching Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices, such as FPGAs, face inefficiencies in switching between processing functions due to the inability to execute a second processing function during the reconfiguration of the circuit in the reconfiguration region, leading to prolonged reconfiguration durations.
Innovation Solution
The implementation of an information processing apparatus that acquires multiple pieces of circuit configuration information for split circuits and executes reconfiguration processes in parallel across multiple partial reconfiguration regions, allowing simultaneous reconfiguration and reduced overall reconfiguration time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the circuit in the reconfiguration region is reconfigured to switch from a first processing function to a second processing function, then the second processing function can be executed, but the device cannot execute processing according to the second processing function during the reconfiguration process, leading to prolonged reconfiguration duration
Solution Approach 1:
The patent divides the reconfiguration region into multiple partial reconfiguration regions (first partial reconfiguration region and second partial reconfiguration region). By segmenting the reconfiguration process into independent parallel regions, the system can reconfigure different parts simultaneously, reducing the total reconfiguration time while maintaining full processing function switching capability.
Solution Approach 2:
The patent prepares circuit configuration information for multiple split circuits in advance and stores it in memory. Before reconfiguration is needed, the configuration data is ready and can be quickly loaded into the partial reconfiguration regions, enabling faster switching between processing functions without extensive on-the-fly configuration processing.
2Loss of time
If multiple pieces of circuit configuration information are acquired and reconfiguration processes are executed in parallel across multiple partial reconfiguration regions, then the overall reconfiguration time is reduced, but the device complexity increases due to multiple configuration management requirements
Solution Approach 1:
The patent combines multiple configuration management functions into a single configuration management unit that handles both first and second partial reconfiguration regions. This unified approach manages the complexity of parallel configuration while maintaining the time-saving benefits of parallel reconfiguration execution.
Solution Approach 2:
The patent introduces a memory component as an intermediary between the configuration management unit and the partial reconfiguration regions. Configuration information is stored in memory and selectively loaded into the appropriate partial reconfiguration regions, simplifying the management of multiple configuration states and reducing the complexity of direct configuration control.
Data Source
AI summary
An information processing apparatus includes a processor configured to: acquire multiple pieces of circuit configuration information corresponding to multiple split circuits forming a processing circuit configured to execute a single processing function; and cause reconfiguration processes that reconfigure multiple partial reconfiguration regions into the multiple split circuits corresponding to the multiple pieces of acquired circuit configuration information to be executed in parallel.