FPGA Deterministic Parallel Routing for Faster Compilation

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Solution Overview

Problem

Traditional FPGA routing algorithms, particularly PathFinder-based methods, are time-consuming and computationally intensive, especially for large and complex designs, and require further enhancements to optimize runtime and solution quality, particularly when using map-based lookahead techniques.

Innovation Solution

A hybrid routing method that integrates deterministic parallel routing with incremental routing, applying parallel processing during initial iterations with high workload and transitioning to sequential routing for subsequent iterations, utilizing a design router that builds non-overlapping routing trees and employs net partitioning techniques to enhance efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If PathFinder-based sequential routing is used, then routing solution quality is maintained, but compilation runtime is excessive

Engineering Contradiction:

Improvecompilation runtimeVSAvoidrouting time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The routing process is segmented into multiple independent iterations, where each iteration routes a subset of nets. This allows parallel execution of iterations without affecting the final routing quality, as each iteration contributes incrementally to the complete routing solution.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The routing algorithm performs preliminary actions by establishing initial routing trees for each net in parallel before refining them through subsequent iterations. This preliminary parallel routing establishes a foundation that can be improved upon without re-doing the entire routing process sequentially.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If parallel routing is implemented, then compilation runtime is reduced, but routing determinism becomes unpredictable

Engineering Contradiction:

Improverouting speedVSAvoidrouting determinism

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The system dynamically adjusts the routing process by allowing different iterations to execute in parallel while maintaining a deterministic overall structure. The number of iterations and their parallel execution can be adapted based on resource availability, while the routing quality and determinism are preserved through controlled convergence criteria.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20260050726A1System and method for designing a field programmable gate array with deterministic parallel routing

Publication Date: 2026.02.19 KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS

AI summary

A field-programmable gate array (FPGA) routing tool within a computer-aided design system. The tool includes an input device for receiving a netlist containing nets with source nodes, sink nodes, and intermediate nodes at fixed positions. The tool further includes a processing circuitry configured with a design router responsible for constructing non-overlapping routing trees for all nets, ensuring connections from source nodes to sink nodes without exceeding fixed routing resource capacity of the FPGA. The design router utilizes incremental routing, which applies deterministic parallel routing to a window of initial iterations with high routing workload and sequential routing to subsequent iterations. Additionally, a display device is provided to continuously exhibit interconnections and routing utilization during the determination of routing trees.