Parallel FPGA Synthesis via Observer Logic Segmentation
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Solution Overview
Problem
Existing electronic design automation (EDA) tools for field programmable gate arrays (FPGAs) face challenges in optimizing system design settings, as the effectiveness of settings is often unknown until after synthesis, and current methods lack efficient parallel processing for identifying and merging high-quality logic sections.
Innovation Solution
The implementation of observer logic to identify and mark sections of logic, allowing for parallel synthesis runs on separate processors, which analyze and merge the best quality sections based on criteria like size and speed, creating a merged cell netlist.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple synthesis runs are performed with different EDA tool settings to find optimal design quality, then the quality of logic sections can be improved, but the synthesis time and computational resources increase significantly
Solution Approach 1:
The design is divided into multiple sections using observer logic markers. Each section is independently synthesized and evaluated, allowing parallel processing of different design portions with different EDA tool settings, thereby reducing overall synthesis time while maintaining quality optimization.
Solution Approach 2:
Observer logic is inserted into the design before synthesis to pre-identify and mark sections of interest. This preliminary action enables the synthesis tool to focus on specific sections rather than the entire design, reducing the computational burden and time required for multiple synthesis runs.
2Manufacturing precision
If EDA tool settings are applied to the entire design to optimize specific portions, then the quality of those portions can be improved, but the complexity of managing settings increases
Solution Approach 1:
Different EDA tool settings can be applied to different sections of the design by associating settings with specific observer logic markers. This allows localized optimization of logic sections without requiring complex global setting management, as each section can have its own optimized settings independent of others.
3Productivity
If parallel synthesis runs are performed on separate processors, then the synthesis speed can be improved, but the coordination and merging of results becomes more complex
Solution Approach 1:
Observer logic serves as an intermediary that standardizes the interface between parallel synthesis runs and the merging process. By marking sections with consistent observer logic across all parallel runs, the merging of results becomes systematic and automated, reducing the complexity of coordinating multiple processors and combining their outputs.
Data Source
AI summary
A method for designing a system to be implemented on a target device includes performing a first synthesis run on an entire design of a system with a first setting to generate a first cell netlist for the entire design of the system. A second synthesis run is performed on the entire design for the system with a second setting and is performed in parallel with the first synthesis procedure to generate a second cell netlist for the entire design of the system. A merged cell netlist is generated that includes a first section of logic from the first netlist and a second section of logic from the second cell netlist.