FPGA Partial Datapath Processing with External Data Alignment
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Solution Overview
Problem
Existing integrated circuits face challenges in efficiently processing and managing data streams by selectively processing only a portion of the data while ignoring or discarding other portions, particularly in scenarios where a field programmable gate array (FPGA) has a configurable path but other circuitry has a fixed path, leading to inefficiencies in data alignment and combination.
Innovation Solution
The integration of an FPGA and an ASIC within an integrated circuit, where the FPGA processes a first portion of the data stream and the ASIC's data alignment circuitry temporarily stores and synchronizes the second portion, allowing for the generation of a partially processed data stream by combining the processed and unprocessed portions through data combining circuitry, which can perform OR logic or concatenation operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the FPGA processes only a first portion of the data stream while other circuitry processes the second portion, then processing efficiency is improved by selective processing, but data alignment and synchronization become more complex
Solution Approach 1:
The patent introduces data alignment circuitry as an intermediary component that receives the second portion of the data stream, temporarily stores it in buffers, and synchronizes it with the processed first portion. This mediator handles the complexity of alignment, allowing the FPGA and other circuitry to operate independently and efficiently on their respective data portions without direct coordination overhead.
Solution Approach 2:
The data stream is segmented into a first portion and a second portion that can be processed independently. The first portion is processed by the FPGA while the second portion is handled by other circuitry with fixed data paths. This segmentation allows each component to optimize its processing without interfering with the other, improving overall processing efficiency while the data alignment circuitry manages the recombination.
2Adaptability or versatility
If the FPGA has a configurable path for data processing, then adaptability is improved, but processing speed may be reduced compared to fixed path circuitry
Solution Approach 1:
The system segments the data stream into portions processed by the configurable FPGA and portions processed by fixed-path circuitry. The fixed-path circuitry handles the second portion at high speed, while the FPGA provides adaptability for the first portion. This segmentation allows the system to achieve both configurability and high-speed processing by assigning different portions to different processing architectures.
Solution Approach 2:
The patent merges the outputs of the configurable FPGA processing and the fixed-path circuitry processing through data combining circuitry. The data alignment circuitry ensures that the processed first portion and the second portion are properly synchronized and aligned before being combined into the final output stream, thus achieving both adaptability and speed.
3Productivity
If the FPGA processes data in real-time while other circuitry processes the remaining data, then processing throughput is improved, but data synchronization becomes more difficult
Solution Approach 1:
The data alignment circuitry acts as a mediator that receives the second portion of the data stream from other circuitry and temporarily stores it in buffers. It then synchronizes this data with the processed first portion from the FPGA, ensuring reliable data alignment and synchronization. This intermediary approach maintains high throughput while ensuring data integrity and proper synchronization.
Solution Approach 2:
The data alignment circuitry performs preliminary actions by temporarily storing the second portion of the data stream in buffers before it needs to be combined with the processed first portion. This advance preparation and buffering allows the system to handle variable processing times and maintain reliable synchronization without affecting the overall throughput of the parallel processing architecture.
Data Source
AI summary
An integrated circuit including an FPGA having an input to receive an input data stream which includes a first portion and a second portion, processing circuitry to generate processed data by processing only the first portion of the input data stream via a data processing operation, and an output to output the processed data. The integrated circuit further includes logic circuitry, separate from the FPGA, including an input to receive the input data stream, data alignment circuitry to temporally synchronize the second portion of the input data stream with the processing of the first portion of the input data stream via the processing circuitry, and data combining circuitry to generate an output data stream using the processed data from the FPGA and the second portion of the input data stream received from the data alignment circuitry.