FPGA Partial Reconfiguration via Dynamic Resource Allocation
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Solution Overview
Problem
Current methods for adapting control units with programmable logic modules, such as FPGAs, are inefficient due to the need for sequential processing, fixed partition interfaces, and resource wastage, making it difficult to implement changes to logic functions without reconfiguring the entire circuit.
Innovation Solution
A method that reads the initial configuration, replaces or reconfigures specific logic elements, and creates a modified bitstream for writing back to the FPGA, allowing for incremental changes without recompiling the entire circuit, using assignment information to determine transfer points and placing additional logic elements for efficient signal paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the entire FPGA circuit is reconfigured to adapt logic functions, then the logic functions can be changed, but the time consumption increases due to complete synthesis and optimization of placement and routing
Solution Approach 1:
The patent divides the FPGA configuration into multiple partitions, allowing individual logic functions to be reconfigured independently without affecting the entire circuit. This segmentation enables selective reconfiguration of only the modified logic function, significantly reducing the time required compared to complete circuit reconfiguration.
Solution Approach 2:
The patent extracts the specific logic function that needs modification from the overall circuit and processes it separately. By isolating the target logic function and its associated placement and routing information, the system can perform synthesis and optimization only on this extracted portion, avoiding the time-consuming process of processing the entire circuit.
2Adaptability or versatility
If partition interfaces are planned and implemented in the initial design to enable partial reconfiguration, then logic functions can be changed in the second partition, but resources remain unused due to the necessary reservation of the largest assumed number of required logic elements
Solution Approach 1:
The patent implements dynamic resource allocation within partitions, allowing the number and type of logic elements to be adjusted based on the actual requirements of the implemented functionality. Instead of reserving a fixed number of logic elements in advance, the system dynamically allocates resources as logic functions are configured and changed, ensuring that logic elements are only reserved when actually needed.
3Adaptability or versatility
If all logic functions on the first partition remain fixed to enable partial reconfiguration, then the second partition can be reconfigured, but space and energy are consumed by fixed functions even when not required
Solution Approach 1:
The patent makes logic functions on the first partition dynamic rather than fixed, allowing them to be reconfigured or deactivated based on actual system requirements. This enables the system to reduce energy consumption by disabling or reconfiguring logic functions on the first partition when they are not needed, while still maintaining the capability for partial reconfiguration of the second partition.
Data Source
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AI summary
In a method for modifying the configuration of a programmable logic block, an initial configuration of the programmable logic block is read in, such that a logic description, in particular a placed netlist, of the initial configuration is at least partially available. From the logic description of the initial configuration of the programmable logic block, one or more logic elements and/or interconnects are replaced or reconfigured, and a logic description of a target configuration is created which has no or several additional logic elements, and where no or several elements of the initial configuration are missing in the target configuration.Based on mapping information, transfer points are determined, i.e., logic elements, in particular registers, and/or interconnects present in the target and output configurations, at which a modified logic function is applied in the target configuration. At least the logic elements of the programmable logic block that are not already used in the output configuration are marked as free. The additional logic elements of the target configuration are placed on top of the logic elements marked as free and connected to the transfer points via unused interconnects. A modified bitstream is created from the logic description of the target configuration and written to the programmable logic block.