Pattern-Based FPGA Logic Block Fast Interconnections
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing Field Programmable Gate Array (FPGA) architectures face limitations due to the restrictive fanout of Basic Logic Elements (BLEs), which prolong critical paths and reduce performance, especially in control-intensive circuits, as they force combinational outputs to pass through a 2:1 multiplexer, limiting the efficiency of logic blocks and clustering algorithms.
Innovation Solution
A novel pattern-based logic block organization with fast interconnections between Look-Up Tables (LUTs) and a corresponding clustering algorithm that creates groups of LUTs with fast combinational shortcuts, allowing for efficient routing and packing of LUTs into logic blocks, thereby enhancing performance and reducing wire length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If LUTs are connected through the standard 2:1 multiplexer routing architecture, then routing flexibility is maintained, but the critical path length increases and performance decreases
Solution Approach 1:
The patent segments the routing architecture by introducing dedicated fast combinational interconnection paths separate from the standard multiplexer-based local routing. This creates distinct routing segments: fast direct connections for combinational logic within logic blocks, and multiplexer-based routing for other connections, allowing signals to take the shortest path when possible
Solution Approach 2:
The patent introduces fast combinational interconnection structures as intermediary pathways between LUTs within the same logic block. These intermediaries provide direct routing bypassing the 2:1 multiplexer, effectively creating a shortcut layer that reduces critical path length for combinational operations
2Speed
If fast combinational interconnections are added between LUTs, then performance improves, but area overhead increases
Solution Approach 1:
The patent merges the fast combinational interconnection functionality with the existing logic block structure. The fast interconnections are integrated within the logic block boundaries, sharing physical space and resources with other logic block components, thereby minimizing the additional area required
Solution Approach 2:
The patent applies fast combinational interconnections locally within logic blocks rather than globally across the entire FPGA. This localized approach ensures that the area overhead is confined to individual logic blocks and does not propagate across the whole device, making the area penalty manageable and localized
3Productivity
If the clustering algorithm packs LUTs into standard BLEs with single fanout, then routing simplicity is maintained, but logic block efficiency decreases
Solution Approach 1:
The patent makes the clustering algorithm dynamic by introducing pattern recognition capabilities that adapt to different circuit types. The algorithm dynamically selects between standard packing and fast interconnection patterns based on the specific circuit requirements, such as identifying control-intensive circuits that would benefit from fast combinational paths
Solution Approach 2:
The patent changes the packing parameters by introducing new pattern types that utilize fast combinational interconnections. The clustering algorithm now operates with extended parameters including pattern matching criteria, fast interconnection utilization metrics, and circuit-type classification parameters, enabling more efficient packing for specific application domains
Data Source
AI summary
A routing architecture for fast interconnections between Look-Up Tables (LUTs) in a group of Basic Logic Elements (BLEs), whereby a size of the group ranges from 1 to k+1, where k is the number of inputs of a LUT, and LUTs in the group are indexed from 1 to k+1, and whereby (a) an output of a LUTi, 1≤i≤k, connects to one of the inputs of routing multiplexers of LUTj, i<j≤k+1, hence creating a fast interconnection between LUTs, each routing multiplexer of LUTm, 2≤m≤k+1, has only one input that is connected to the output of an other LUT, the output of LUT(k+1) being devoid of any connection to any one of the inputs of the routing multiplexers; (b) a subset of the inputs of LUT1 are connected to the outputs of other LUTs by means of fast interconnections, leaving the remaining inputs of LUT1 free of any fast interconnection, whereby for LUTp, 2≤p≤k+1, p−1 inputs of the LUTp are connected to the outputs of LUTq, 1≤q≤j, by means of fast interconnections; and (c) a cluster-based logic block contains at least one group of LUTs.