FPGA-Based PCIe AIC SSD Protocol Detection
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Solution Overview
Problem
Implementing FPGA-based PCIe AIC SSDs that can support both NVMe and NVMe-oF protocols without modifying existing PCIe IP is challenging due to fast link training requirements and the need to determine the chassis type and protocol operation, which can lead to violations of PCIe link training periods.
Innovation Solution
A single FPGA-based PCIe AIC SSD that can operate in both NVMe and NVMe-oF modes by detecting product information from known locations, such as the U.2 connector's chassis type pin, and configuring the PCIe interface independently of the FPGA, allowing operation across various Ethernet speeds without hardware changes, and fitting into existing SSD form factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA-based PCIe AIC SSD implements both NVMe and NVMe-oF protocols with protocol detection, then protocol versatility is improved, but link training time may be violated
Solution Approach 1:
The patent applies preliminary action by performing protocol detection and chassis type identification before PCIe link training begins. The system detects product information from known locations (such as chassis type pins on U.2 connectors) in advance, determines the appropriate protocol (NVMe or NVMe-oF) beforehand, and configures the PCIe interface independently of FPGA initialization. This preliminary protocol determination prevents time violations during the actual link training process.
Solution Approach 2:
The patent segments the initialization process into distinct phases: (1) protocol detection phase using chassis type pins before link training, (2) PCIe interface configuration phase independent of FPGA, and (3) link training phase. This segmentation allows protocol determination to occur separately from the time-critical link training process, resolving the contradiction between protocol versatility and link training time constraints.
2Loss of time
If PCIe interface is configured independently of FPGA, then link training time compliance is improved, but device complexity increases
Solution Approach 1:
The patent extracts the PCIe interface configuration process from the FPGA initialization sequence. By taking out the PCIe configuration step and making it independent of FPGA programming and initialization, the system ensures that PCIe link training can proceed within required time limits without waiting for complex FPGA setup. This extraction reduces the critical path timing while managing overall device complexity through structured initialization sequences.
3Speed
If product information is detected from known locations, then protocol determination speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies self-service by using the chassis type pins on standard connectors (such as U.2 connectors) that are already present in the deployment environment. The system detects product information from these existing structural features without requiring additional manufacturing steps or precision components. This approach leverages the existing connector infrastructure to provide rapid protocol detection while avoiding increased manufacturing precision requirements.
Data Source
AI summary
According to some example embodiments according to the present disclosure, a device includes a printed circuit board (PCB); a solid state drive (SSD) connected at a first side of the PCB via at least one SSD connector; at least one field programmable gate array (FPGA) attached to the PCB at a second side of the PCB; and at least one front end connector attached to the PCB at a third side of the PCB, wherein the device is configured to process data stored in the SSD based on a command received via the at least one front end connector.